Table 5-1. Pin Functions (continued)

PIN

I/O TYPE(2)

DESCRIPTION

NAME

NO.

SADR1

8

I, S, PU / PD

SMBus address strap bit[1]. This is a 3-level input that is decoded in conjunction

with pin B4 to set SMBus address. It has internal 120-kΩ pullup / pulldown network

biasing to VDD/2 when no connect.

For a high-level input configuration, the pin should be pulled up to 3.3-V VDD

through an external pullup resistor from 1k to 5k with 5% tolerance.

For a low-level input configuration, the pin should be pulled down to ground

through an external pulldown resistor from 1k to 5k with 5% tolerance.

For a mid-level input configuration, the pin should be left floating and not

connected to VDD or ground.

SMBWRTLOCK

46

I, PD

SMBWRTLOCK: Disables write commands on SMBus. All writes will be ignored

when SMBWRTLOCK is asserted (reads are not affected). Internal 180-kΩ

pulldown, active low

0 = SMBus write enabled.

1 = SMBus write disabled.

SUPPLY VOLTAGE AND GROUND

VDDR

2

P

Power supply input for input clock receiver. Connect to 3.3-V power supply rail with

decoupling capacitor to GND. Place a 0.1-µF capacitor close to each supply pin

between power supply and ground.

VDD

11, 15, 19, 27, 34,

38, 42, 44

P

3.3-V power supply for output channels and core voltage.

GND

DAP

G

Ground. Connect ground pad to system ground.

NO CONNECT

NC

9, 10, 20, 43, 45,

47, 48

—

Do not connect to GND or VDD.

(1)

The “#” symbol at the end of a pin name indicates that the active state occurs when the signal is at a low voltage level. When “#” is not

present, the signal is active high.

(2)

The definitions below define the I/O type for each pin.

•

I = Input

•

O = Output

•

I / O = Input / Output

•

PU / PD = Internal 180-kΩ Pullup / Pulldown network biasing to VDD/2

•

PD = Internal 180-kΩ Pulldown

•

S = Hardware Configuration Pin

•

P = Power Supply

•

G = Ground

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CDCDB803

SNAS820 – AUGUST 2021

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