56F8335 datasheet(53/160 Pages) FREESCALE

53 / 160 page

Peripheral Memory Mapped Registers

56F8335 Technical Data, Rev. 1

Freescale Semiconductor

Preliminary

Table 4-18 Quadrature Decoder 1 Registers Address Map

(DEC1_BASE = $00 F190)

Quadrature Decoder 1 is NOT available in the 56F8135 device

Address Offset

DEC1_DECCR

Decoder Control Register

DEC1_FIR

Filter Interval Register

DEC1_WTR

Watchdog Time-out Register

DEC1_POSD

Position Difference Counter Register

DEC1_POSDH

Position Difference Counter Hold Register

DEC1_REV

Revolution Counter Register

DEC1_REVH

Revolution Hold Register

DEC1_UPOS

Upper Position Counter Register

DEC1_LPOS

Lower Position Counter Register

DEC1_UPOSH

Upper Position Hold Register

DEC1_LPOSH

Lower Position Hold Register

DEC1_UIR

Upper Initialization Register

DEC1_LIR

Lower Initialization Register

DEC1_IMR

Input Monitor Register

Table 4-19 Interrupt Control Registers Address Map

(ITCN_BASE = $00 F1A0)

Address Offset

IPR 0

Interrupt Priority Register 0

IPR 1

Interrupt Priority Register 1

IPR 2

Interrupt Priority Register 2

IPR 3

Interrupt Priority Register 3

IPR 4

Interrupt Priority Register 4

IPR 5

Interrupt Priority Register 5

IPR 6

Interrupt Priority Register 6

IPR 7

Interrupt Priority Register 7

IPR 8

Interrupt Priority Register 8

IPR 9

Interrupt Priority Register 9

VBA

Vector Base Address Register

FIM0

Fast Interrupt Match Register 0

FIVAL0

Fast Interrupt Vector Address Low 0 Register

56F8335 Datasheet(PDF) 53 Page - Freescale Semiconductor, Inc

56F8335 Datasheet(HTML) 53 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL