ML9059 datasheet(21/72 Pages) OKI

21 / 72 page

PEDL9059-02

OKI Semiconductor

ML9059

21/72

Serial Interface

When the serial interface is selected (P/S = “L”), the serial data input (SI) and the serial clock input (SCL) can be

accepted if the chip is in the active state (CS1 = “L” and CS2 = “H”). The serial interface consists of an 8-bit shift

DB0 at the rising edge of the serial clock input, and is converted into parallel data at the rising edge of the 8th serial

clock pulse and processed further. The identification of whether the serial data is display data or command is

judged based on the A0 input, and the data is treated as display data when A0 is “H” and as command when A0 is

“L”. The A0 input is read in and identified at the rising edge of the (8

× n) th serial clock pulse after the chip has

become active. Fig. 1 shows the signal chart of the serial interface. (When the chip is not active, the shift register

and the counter are reset to their initial states. No data read out is possible in the case of the serial interface. It is

necessary to take sufficient care about wiring termination reflection and external noise in the case of the SCL

signal. We recommend verification of operation in an actual unit.)

Fig. 1 Signal chart during serial interface

• Chip select

The ML9059 has the two chip select pins CS1and CS2, and the MPU interface or the serial interface is enabled

only when CS1 = “L” and CS2 = “H”. When the chip select signals are in the inactive state, the DB0 to DB7 lines

will be in the high impedance state and the inputs A0, RD, and WR will not be effective. When the serial interface

has been selected, the shift register and the counter are reset when the chip select signals are in the inactive state.

• Accessing the display data RAM and the internal registers

Accessing the ML9059 from the MPU side requires merely that the cycle time (tCYC) be satisfied, and high speed

data transfer without requiring any wait time is possible. Also, during the data transfer with the MPU, the ML9059

carries out a type of pipeline processing between LSIs via a bus holder associated with the internal data bus. For

example, when the MPU writes data in the display data RAM, the data is temporarily stored in the bus holder, and

is then written into the display data RAM before the next data read cycle. Further, when the MPU reads out data in

the display data RAM, first a dummy data read cycle is carried out to temporarily store the data in the bus holder

which is then placed on the system bus and is read out during the next read cycle. There is a restriction on the read

sequence of the display data RAM, which is that the read instruction immediately after setting the address does not

read out the data of that address, but that data is output as the data of the address specified during the second data

read sequence, and hence care should be taken about this during reading. Therefore, always one dummy read is

necessary immediately after setting the address or after a write cycle: (The status read cannot use dummy read

cycles.) This relationship is shown in Figs 2(a) and 2(b).

DB7

SCL

CS2

CS1

DB6

DB5

DB4

DB3

DB2

DB1

DB0

DB7

DB6

DB5

DB4

DB3

DB2

ML9059 Datasheet(PDF) 21 Page - OKI electronic componets

ML9059 Datasheet(HTML) 21 Page - OKI electronic componets

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72

Datasheet Download

Link URL