ML9059 datasheet(11/72 Pages) OKI

11 / 72 page

PEDL9059-02

OKI Semiconductor

ML9059

11/72

[VDD = 4.5 to 5.5 V, Tj = –40 to +85°C]

Rated value

Parameter

Symbol

Condition

Min

Max

Unit

Address hold time

tAH6

—

Address setup time

tAW6

—

System cycle time

tCYC6

166

—

Data setup time

tDS6

—

Data hold time

tDH6

—

Access time

tACC6

CL = 100 pF

—

Output disable time

tOH6

Read

tEWHR

—

Enable H pulse width

Write

tEWHW

—

Read

tEWLR

—

Enable L pulse width

Write

tEWLW

—

[VDD = 3.7 to 4.5 V, Tj = –40 to +85°C]

Rated value

Parameter

Symbol

Condition

Min

Max

Unit

Address hold time

tAH6

—

Address setup time

tAW6

—

System cycle time

tCYC6

300

—

Data setup time

tDS6

—

Data hold time

tDH6

—

Access time

tACC6

—

140

Output disable time

tOH6

CL = 100 pF

100

Read

tEWHR

120

—

Enable H pulse width

Write

tEWHW

—

Read

tEWLR

—

Enable L pulse width

Write

tEWLW

—

Note 1: The input signal rise and fall times are specified as 15ns or less.

When using the system cycle time for fast speed, the specified values are (tr + tf)

≤ (t

CYC6 – tEWLW – tEWHW)

or (tr + tf)

≤ (t

CYC6 – tEWLR – tEWHR).

Note 2: All timings are specified taking the levels of 20% and 80% of VDD as the reference.

Note 3: The values of tEWLW and tEWLR are specified during the overlapping period of CS1 at “L” (CS2 = “H”) and

the “H” level of E.

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