ML9059 datasheet(13/72 Pages) OKI

13 / 72 page

PEDL9059-02

OKI Semiconductor

ML9059

13/72

[VDD = 3.7 to 4.5 V, Tj = –40 to +85°C]

Rated value

Parameter

Symbol

Condition

Min

Max

Unit

Serial clock period

tSCYC

250

—

SCL “H” Pulse width

tSHW

100

—

SCL “L” Pulse width

tSLW

100

—

Address setup time

tSAS

150

—

Address hold time

tSAH

150

—

Data setup time

tSDS

100

—

Data hold time

tSDH

100

—

CS setup time

tCSS

150

—

CS hold time

tCSH

150

—

Note 1: The input signal rise and fall times are specified as 15ns or less.

Note 2: All timings are specified taking the levels of 20% and 80% of VDD as the reference.

• Display control output timing

CL(OUT)

tDFR

VOH

VIH

VIL

[VDD = 4.5 to 5.5 V, Tj = –40 to +85°C]

Rated value

Parameter

Symbol

Condition

Min

Typ

Max

Unit

FR Delay time

tDFR

CL = 50 pF

—

[VDD = 3.7 to 4.5 V, Tj = –40 to +85°C]

Rated value

Parameter

Symbol

Condition

Min

Typ

Max

Unit

FR Delay time

tDFR

CL = 50 pF

—

Note 1: All timings are specified taking the levels of 20% and 80% of VDD as the reference.

Note 2: Valid only when the device operates in master mode.

ML9059 Datasheet(PDF) 13 Page - OKI electronic componets

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