Data Sheet

AD4116

Rev. 0 | Page 57 of 59

Bits

Bit Name

Settings

Description

Reset

Access

[9:8]

INBUFx

Input Buffer. This bit enables or disables input buffers.

0x0

R/W

00

Disabled.

01

Reserved.

10

Reserved.

11

Enabled.

[7:6]

Reserved

This bit is reserved. Set this bit to 0.

0x0

R

[5:4]

REF_SELx

These bits allow the user to select the reference source for ADC conversion on

Setup 0.

0x0

R/W

00

External reference − REF±.

10

Internal 2.5 V reference must be enabled via ADCMODE (see Table 27).

11

AVDD − AVSS.

[3:0]

Reserved

These bits are reserved. Set these bits to 0.

0x0

R

FILTER CONFIGURATION REGISTER 0 TO FILTER CONFIGURATION REGISTER 7

Address: 0x28 to 0x2F, Reset: 0x0500, Name: FILTCON0 to FILTCON7

The filter configuration registers are 16-bit registers that configure the ADC data rate and filter options. Writing to any of these registers resets

any active ADC conversion and restarts converting at the first channel in the sequence. The layout for FILTCON0 to FILTCON7 is identical.

Table 35. Bit Descriptions for FILTCON0 to FILTCON7

Bits

Bit Name

Settings

Description

Reset

Access

15

SINC3_MAPx

If this bit is set, the mapping of the filter register changes to directly program the

decimation rate of the sinc3 filter for Setup 0. All other options are eliminated. This bit

allows fine tuning of the output data rate and filter notch for rejection of specific

0x0

R/W

[14:12]

Reserved

These bits are reserved. Set these bits to 0.

0x0

R

11

ENHFILTENx

This bit enables various post filters for enhanced 50 Hz/60 Hz rejection for Setup 0. The

ORDER0 bits must be set to 00 to select the sinc5 + sinc1 filter for this function to work.

0x0

R/W

0

Disabled.

1

Enabled.

[10:8]

ENHFILTx

These bits select between various post filters for enhanced 50 Hz/60 Hz rejection

for Setup 0.

0x5

R/W

010

27 SPS, 47 dB rejection, and 36.7 ms settling.

011

25 SPS, 62 dB rejection, and 40 ms settling.

101

20 SPS, 86 dB rejection, and 50 ms settling.

110

16.67 SPS, 92 dB rejection, and 60 ms settling.

7

Reserved

This bit is reserved. Set this bit to 0.

0x0

R

[6:5]

ORDERx

These bits control the order of the digital filter that processes the modulator data for

Setup 0.

0x0

R/W

00

Sinc5 + sinc1 (default).

11

Sinc3.

[4:0]

ODRx

These bits control the output data rate of the ADC and, therefore, the settling time

and noise for Setup x. Rates shown are for single channel enabled sinc5 + sinc 1 filter.

See Table 7 for multiple channels enabled.

0x0

R/W

00000

62500 SPS.

00001

62500 SPS.

00010

62500 SPS.

00011

62500 SPS.

00100

31250 SPS.

00101

31250 SPS.

00110

15625 SPS.

00111

10416.7 SPS.

01000

5194.8 SPS (5208.3 SPS for sinc3).

01001

2496.9 SPS (2500 SPS for sinc3).

01010

1007.6 SPS (1008.1 SPS for sinc3).

01011

499.9 SPS (500 SPS for sinc3).