Data Sheet

AD4116

Rev. 0 | Page 7 of 59

TIMING CHARACTERISTICS

IOVDD = 2 V to 5.5 V (single-supply), IOVDD = 2 V to 3.6V (split-supply), Input Logic 0 = 0 V, Input Logic 1 = IOVDD, and capacitive

Table 2.

Parameter

Unit

SCLK

25

ns min

SCLK high pulse width

25

ns min

SCLK low pulse width

READ OPERATION

0

ns min

CS falling edge to DOUT/RDY active time

15

ns max

IOVDD = 4.75 V to 5.5 V

40

ns max

IOVDD = 2 V to 3.6 V

0

ns min

12.5

ns max

IOVDD = 4.75 V to 5.5 V

25

ns max

IOVDD = 2 V to 3.6 V

2.5

ns min

Bus relinquish time after CS inactive edge

20

ns max

0

ns min

SCLK inactive edge to CS inactive edge

10

ns min

SCLK inactive edge to DOUT/RDY high/low

WRITE OPERATION

0

ns min

8

ns min

Data valid to SCLK edge setup time

8

ns min

Data valid to SCLK edge hold time

5

ns min

CS rising edge to SCLK edge hold time

1

Sample tested during initial release to ensure compliance.

2

See Figure 2 and Figure 3.

3

4

The SCLK active edge is the falling edge of SCLK.

5

DOUT/RDY returns high after a read of the data register. In single conversion mode and continuous conversion mode, the same data can be read again, if required,

while DOUT/RDY is high. However, care must be taken to ensure that subsequent reads do not occur close to the next output update. If the continuous read feature is

enabled, the digital word can be read only once.