LT3757 datasheet(13/38 Pages) AD

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LTC7840

Rev 0

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circuit current, but the other regulators are off. This would

place a thermal burden on the highest output voltage LDO

and could cause the maximum die temperature to be

exceeded. In multi-chip parallel applications, each LDO

output should be independently bypassed to its respective

GND pin as close as possible to each IC.

The Gate Driver Supply LDO (DRVCC)

The 10V output (DRVCC) of the first LDO is powered from

VIN and supplies power to the power MOSFET gate driv-

ers. The DRVCC pin should be bypassed to PGND with

a minimum of 4.7µF ceramic capacitor (X5R or better)

placed as close as possible to the IC pin. If two power

MOSFETs are connected in parallel for each channel in

order to increase the output power level, or if a single

MOSFET with a Qg greater than 50nC is used, then it is

recommended that the bypass capacitor be increased to

a minimum of 10µF.

An under voltage lockout (UVLO) circuit senses the DRVCC

regulator output in order to protect the power MOSFETs

from operating with the inadequate gate drive. For the

LTC7840, the rising UVLO threshold is 4.4V and the hys-

teresis is typically 500mV. In low VIN applications, the

low threshold MOSFET (<3.5V) may be used. In high VIN

applications, higher UVLO may be programmed as shown

in Figure 5. The LTC7840 is optimized for high voltage

power MOSFETs with RDS(ON) ratings at a VGS of 6V.

The Low Voltage Analog and Digital Supply LDO

(INTVCC)

The second LDO within the LTC7840 is powered from

DRVCC and serves as the supply to the low voltage analog

and digital control circuitry. The output (INTVCC) voltage

of this LDO is 3.8V. The INTVCC pin should be bypassed to

SGND with a 1nF ceramic capacitor (X5R or better) placed

as close as possible to the IC pin. This LDO is not intended

to be used as a supply for external circuitry.

Thermal Considerations and Package Options

The LTC7840 is offered in two package options. The

28-lead thermally enhanced TSSOP package (FE28) has a

thermal resistance RTH(JA) of 30ºC/W, and the 4mm x 5mm

28-lead QFN package (UFD28) has a thermal resistance of

47ºC/W. The TSSOP package has a lead pitch of 0.65mm,

whereas the QFN package has a lead pitch of 0.5mm.

The DRVCC LDO can supply up to 100mA current. As a

result, care must be taken to ensure that the maximum

junction temperature of the IC should not be exceeded.

The junction temperature can be estimated by the follow-

ing equations:

IQ(TOT) = IQ + QG(TOT) • f

PDISS = VIN • (IQ + QG(TOT) • f

TJ = TA + PDISS • RTH(JA)

The total quiescent current (IQ(TOT)) consists of the static

supply current (IQ) and the current required to charge

the gate capacitance of the power MOSFETs. The value

of QG(TOT) should come from the plot of VGS vs QG in

the Typical Performance Characteristics section of the

MOSFET data sheet. The value listed in the electrical

specifications may be measured at a higher VGS, such as

15V, whereas the value of interest is at the 10V DRVCC

gate drive voltage.

As an example of the required thermal analysis, consider a

2-phase boost converter with a 5.5V to 24V input voltage

range and an output voltage of 72V at 1.5A. The switching

frequency is 150kHz and the maximum ambient tempera-

ture is 70°C. The power MOSFET used for this application

is the Renesas HAT2267H, which has a typical RDS(ON)

of 13mΩ at VGS = 10V. From the plot of VGS vs QG, the

total gate charge at VGS = 10V is 30nC (the temperature

coefficient of the gate charge is low). One power MOSFET

is used for each phase. For the QFN package option:

IQ(TOT) = 3mA + 2 • 30nC • 150kHz = 12mA

PDISS = 24V • 12mA = 288mW

TJ = 70°C + 288mW • 30°C/W = 78.64°C

In this example, the junction temperature rise is only

8.64°C. These equations demonstrate how the gate

charge current typically dominates the quiescent current

of the IC, and how the choice of package option and board

heat sinking can have a significant effect on the thermal

performance of the solution.

OPERATION

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