LT3757 datasheet(29/38 Pages) AD

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LTC7840

Rev 0

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between two or more inductors. Nonetheless, significant

stress can be placed on the input capacitor, especially

in high duty cycle applications. Figure 18 illustrates the

normalized input ripple current, where:

INORM =

VIN

L • f

Figure 18.

DUTY CYCLE

1.00

0.90

0.80

0.60

0.70

0.50

0.40

0.30

0.20

0.10

0.8

7840 F18

0.2

0.4

0.6

1.0

1-PHASE

2-PHASE

Normalized Input Peak-to-Peak Ripple Current

Soft Start (SS Pin) Capacitor Selection

The LTC7840 has hiccup mode to protect the system in

the event of overcurrent. Because the hiccup mode timing

is set by discharging the soft start capacitor, at least 0.1µF

capacitor must be tied between SS pin and SGND. At start

up, an 10µA current flowing out of SS pin to charge the

soft start capacitor. The hiccup mode is disabled until the

voltage on SS pin ramps up to 1.32V (10% higher than

the 1.2V internal reference). For a properly configured

system, the output’s feedback voltage tracks the voltage

on SS pin until it reaches 1.2V. At this moment, the con-

verter’s output voltage reaches the regulated value and the

system enters the steady state. If the target output voltage

is high or if heavy loaded, the soft start capacitor needs to

be larger to slow down the ramp up speed, otherwise, the

converter’s output voltage cannot follow the voltage on SS

pin in time. At the same time, the system keeps operating

at the maximum current limit. This situation is thought

as overcurrent event by the controller. Once the voltage

on SS pin reaches 1.32V, the hiccup mode is enabled to

make the converter enter the sleep mode even though

the output voltage hasn’t reached the target value. In this

case, the system cannot start up normally.

Checking the Load Transient Response

The regulator loop response can be checked by looking at

the load current transient response. Switching regulators

take several cycles to respond to a step in DC (resistive)

load current. When a load step occurs, VOUT shifts by an

amount equal to ∆ILOAD • (ESR), where ESR is the effective

series resistance of COUT. ∆ILOAD also begins to charge or

discharge COUT, generating the feedback error signal that

forces the regulator to adapt to the current change and

return VOUT to its steady-state value. During this recovery

time VOUT can be monitored for excessive overshoot or

ringing, which would indicate a stability problem.

The availability of the ITH pin not only allows optimization

of control loop behavior but also provides a DC coupled

and AC filtered closed loop response test point. The DC

step, rise time and settling at this test point truly reflects

the closed loop response. Assuming a predominantly sec-

ond order system, phase margin and/or damping factor

can be estimated using the percentage of overshoot seen

at this pin. The bandwidth can also be estimated by exam-

ining the rise time at the pin.

The ITH series RC • CC filter sets the dominant pole-zero

loop compensation. The transfer function for boost and

flyback converters contains a right half plane zero that nor-

mally requires the loop crossover frequency to be reduced

significantly in order to maintain good phase margin.

The RC • CC filter values can typically be modified slightly

(from 0.5 to 2 times their suggested values) to optimize

transient response once the final PC layout is done and the

particular output capacitor type(s) and value(s) have been

determined. The output capacitor configuration needs to

be selected in advance because the effective ESR and bulk

capacitance have a significant effect on the loop gain and

phase. An output current pulse of 20% to 80% of full-load

current having a rise time of 1μs to 10μs will produce out-

put voltage and ITH pin waveforms that will give a sense

APPLICATIONS INFORMATION

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