LT3757 datasheet(16/38 Pages) AD

16 / 38 page

LTC7840

Rev 0

For more information www.analog.com

OPERATION

Figure 5.

–

RUN

COMPARATOR

1.22V

7840 F05

VIN

LTC7840

RUN

10V

INTERNAL 4.5V

1µA

4.5µA

SGND

BIAS AND

START-UP

CONTROL

Programming the Input Voltage Turn-On

and Turn-Off Thresholds Using the RUN Pin

The start-up of each channel’s output voltage, VOUT, is

controlled by the voltage on its SS pin. When the voltage

on the SS pin is less than the 1.2V internal reference, the

LTC7840 regulates the VFB voltage to the SS pin voltage

instead of the 1.2V reference. This allows the SS pin to

be used to program the soft-start period by connecting

an external capacitor from the SS pin to SGND. An inter-

nal 10µA pull-up current charges this capacitor, creating

a voltage ramp on the SS pin. As the SS voltage rises

linearly from 0V to 1.2V (and beyond), the output volt-

age VOUT rises smoothly from zero to its final value. The

soft-start-up time can be estimated by:

1.2V

10µA

tSTART-UP = CSS •

= 0.12 • CSS

The SS pin has an internal open-drain NMOS pull-down

transistor that turns on when the RUN pin is pulled low,

when the voltage on the INTVCC pin or DRVCC pin is below

its undervoltage lockout threshold, or during an overtem-

perature condition.

Frequency Selection and Phase-Locked Loop

(FREQ and SYNC Pins)

The selection of switching frequency is a trade-off between

efficiency and component size. Low frequency opera-

tion increases efficiency by reducing MOSFET switching

losses, but requires larger inductance and/or capacitance

to maintain low output ripple voltage. The switching fre-

quency of the LTC7840’s controller can be selected using

the FREQ pin. If the SYNC pin is not being driven by an

external clock source, the FREQ pin can be used to pro-

gram the controller’s operating frequency from 50kHz to

425kHz. There is a precision 10µA current flowing out of

the FREQ pin, so the user can program the controller’s

switching frequency with a single resistor to SGND. The

curve in Figure 6 shows the relationship between the volt-

age on the FREQ pin and switching frequency.

A phase-locked loop (PLL) is integrated on the LTC7840

to synchronize the internal oscillator to an external clock

source that is connected to the SYNC pin. The PLL loop

filter network is also integrated inside the LTC7840. The

phase-locked loop is capable of locking to any frequency

within the range of 50kHz to 450kHz. The frequency set-

ting resistor should always be present to set the control-

ler’s initial switching frequency to the same value as the

synchronized frequency before locking to the external

clock. The lock-in time can be minimized by this way. It

also ensures that the operating frequency remains essen-

tially constant in the event the sync signal is lost. The

SYNC pin has an internal 100k resistor to ground.

Figure 6.

VFREQ (V)

0.5

1.5

2.5

100

200

300

400

500

7840 F06

Switching Frequency vs FREQ Pin Voltage

Power Good (PGOOD1, PGOOD2 Pins)

When either feedback voltage is not within ±10% of the

1.2V reference voltage, its respective PGOOD pin is pulled

low. A PGOOD pin will also pull low when its channel is in

the soft-start or UVLO. Both PGOOD pins pull low when

LT3757 Datasheet(PDF) 16 Page - Analog Devices

LT3757 Datasheet(HTML) 16 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38

Datasheet Download

Link URL