HCS12COREUG datasheet(105/124 Pages) MOTOROLA

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MC9S12DT128B Device User Guide — V01.07

105

A.5.3 Phase Locked Loop

The oscillator provides the reference clock for the PLL. The PLL´s Voltage Controlled Oscillator (VCO)

is also the system clock source in self clock mode.

A.5.3.1 XFC Component Selection

This section describes the selection of the XFC components to achieve a good filter characteristics.

Figure A-2 Basic PLL functional diagram

The following procedure can be used to calculate the resistance and capacitance values using typical

values for K1, f1 and ich from Table A-16.

The grey boxes show the calculation for fVCO = 50MHz and fref = 1MHz. E.g., these frequencies are used

for fOSC = 4MHz and a 25MHz bus clock.

The VCO Gain at the desired VCO frequency is approximated by:

The phase detector relationship is given by:

ich is the current in tracking mode.

fosc

refdv+1

fref

Phase

Detector

VCO

synr+1

fvco

Loop Divider

KΦ

∆

fcmp

VDDPLL

XFC Pin

1 e

vco

–

()

⋅

-----------------------

⋅

120

–

()

120

–

------------------------

⋅

= -97.43MHz/V

KΦ

–

⋅

= 341.0Hz/

Ω

HCS12COREUG Datasheet(PDF) 105 Page - Motorola, Inc

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