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LTC4449 Datasheet(PDF) 12 Page - Analog Devices |
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LTC4449 Datasheet(HTML) 12 Page - Analog Devices |
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12 / 14 page ![]() LTC7067 12 Rev. 0 For more information www.analog.com APPLICATIONS INFORMATION Unlike a pure capacitive load, a power MOSFET’s gate capacitance seen by the driver output varies with its VGS voltage level during switching. A MOSFET’s capacitive load power dissipation can be calculated using its gate charge, QG. The QG value corresponding to the MOSFET’s VGS value (VCC in this case) can be readily obtained from the manufacturer’s QG vs VGS curves. For identical MOSFETs on G2 and G1: PQG ≈ 2(QG)(fIN)(VCC) BYPASSING AND GROUNDING The LTC7067 requires proper bypassing on the VCC, VG1VCC-G1RTN and VG2VCC-G2RTN supplies due to its high speed Switching (nanoseconds) and large AC currents (amperes). Careless component placement and PCB trace routingmaycauseexcessiveringingandunder/overshoot. To obtain the optimum performance form the LTC7067: • Mount the bypass capacitors as close as possible between the VCC and SGND pins, the G2VCC and G2RTN pins, and the G1VCC and G1RTN pins. The leads should be shortened as much as possible to reduce lead inductance. • Use a low inductance, low impedance ground place to reduce any ground drop and stray capacitance. Remember that the LTC7067 switches greater than 5A peak currents and any significant ground drop will degrade signal integrity. • Plan the power/ground routing carefully. Know where the large load switching current is coming from and going to. Maintain separate ground return paths for the input pin and the output power stage. • Kelvin connect the G1 pin to the G1 MOSFET gate and G1RTN pin to the G1 MOSFET source. Kelvin connect the G2 pin to the G2 MOSFET gate and G2RTN to the G2 MOSFET source. Keep the copper trace between the driver output pin and load short and wide. • Be sure to solder the Exposed Pad on the back side of the LTC7067 packages to the board. Failure to make good thermal contact between the exposed back side and the copper board will result in thermal resistances far greater than specified for the packages. |
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