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2021 Microchip Technology Inc. and its subsidiaries

DS20006508B-page 5

SY75602A/02B/603A/03B/604A/04B

Clock Source DC Impedance (OUTx_n) for

part with 85Ω embedded differential series

resistance (parts with suffix “A”)

34

—

51

Ω

Note 1, Note 9

Clock Source DC Impedance (OUTx_p) for

part with 100Ω embedded differential series

resistance (parts with suffix “B”)

40

—

60

Ω

Note 1, Note 9

Clock Source DC Impedance (OUTx_n) for

part with 100Ω embedded differential series

resistance (parts with suffix “B”)

40

—

60

Ω

Note 1, Note 9

Output Frequency

0

—

250

MHz —

Output to Output Skew

—

—

30

ps

—

Device to Device Output Skew

—

—

50

ps

—

Input to Output Delay

0.9

1.2

1.5

ns

—

Output Enable Time

—

—

3.5

cycles Note 12

Output Disable Time

—

—

4.5

cycles Note 12

Note 1: Measurement taken from single ended waveform.

2: Measurement taken from differential waveform.

3: Measured from –150 mV to +150 mV on the differential waveform (derived from OUTx_p to OUTx_n). The

signal must be monotonic through the measurement region for rise and fall time. The 300 mV

measurement window is centered on the differential zero crossing. See Figure 1-5.

4: Measured at crossing point where the instantaneous voltage value of the rising edge of OUTx_p equals

the falling edge of OUTx_n. See Figure 1-1.

5: Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is

crossing. Refers to all crossing points for this measurement. See Figure 1-1.

6: Defined as the maximum instantaneous voltage including overshoot. See Figure 1-1.

7: Defined as the minimum instantaneous voltage including undershoot. See Figure 1-1.

8: Defined as the total variation of all crossing voltages of Rising OUTx_p and Falling OUTx_n. This is the

9: System board compliance measurements must use the test load card described in Figure 1-7. OUTx_p

measurements requiring single-ended measurements. Either single-ended probes with math or differential

probe can be used for differential measurements.

See Figure 1-6.

11: Matching applies to rising edge rate for OUTx_p and falling edge rate for OUTx_n. It is measured using a

±75 mV window centered on the median cross point where OUTx_p rising meets OUTx_n falling. The

median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate

calculations. The Rise Edge Rate of OUTx_p should be compared to the Fall Edge Rate of OUTx_n; the

maximum allowed difference should not exceed 20% of the slowest edge rate. See Figure 1-3.

12: Output Enable control pins are synchronous with the input clock and it takes four rising edges before out-

puts get enabled and five rising edges before outputs get disabled. Hence the minimum input frequency is

greater than 0 Hz. Once the outputs are enabled the input clock frequency can be reduced to 0 Hz.

OUTPUT ELECTRICAL CHARACTERISTICS (CONTINUED)

noted.

Parameter

Symbol

Min.

Typ.

Max.

Units Conditions