SY75604B datasheet(6/26 Pages) MICROCHIP

6 / 26 page

SY75602A/02B/603A/03B/604A/04B

DS20006508B-page 6

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2021 Microchip Technology Inc. and its subsidiaries

JITTER AND PHASE NOISE

Parameter

Symbol

Min. Typ. Max.

Units

Conditions

Peak-to-Peak Additive Jitter

p-p AJRMS

—

4.5

Note 1, Note 2

Additive Jitter as per PCIe 1.0

(1.5 MHz to 22 MHz)

tjPCIe_1.0

—

0.7

0.8

psRMS Note 1, Note 2

Additive Jitter as per PCIe 2.0 high band (1.5 MHz

to 50 MHz)

tjPCIe_2.0_high —

fsRMS Note 1, Note 2

Additive Jitter as per PCIe 2.0 low band

(10 kHz to 1.5 MHz)

tjPCIe_2.0_low

—

fsRMS Note 1, Note 2

Additive Jitter as per PCIe 2.0 mid band

(5 MHz to 16 MHz)

tjPCIe_2.0_mid

—

fsRMS Note 1, Note 2

Additive Jitter as per PCIe 3.0

(PLL_BW = 2 to 5 MHz, CDR = 10 MHz)

tjPCIe_3.0

—

fsRMS Note 1, Note 2

Additive Jitter as per PCIe 4.0

(PLL_BW = 2 to 5 MHz, CDR = 10 MHz)

tjPCIe_4.0

—

fsRMS Note 1, Note 2

Additive Jitter as per PCIe 5.0

(PLL_BW = 0.5 to 1.8 MHz, CDR for 32 GT/s CC)

tjPCIe_5.0

—

fsRMS Note 2, Note 3

Additive jitter as per Intel QPI 9.6 Gbps

tjQPI

—

fsRMS Note 1, Note 2

Additive RMS jitter in 1 MHz to 20 MHz band

tj_1M_20M

—

fsRMS

Note 1, Note 2

(100 MHz clock)

—

fsRMS

Note 1, Note 2

(133 MHz clock)

Additive RMS jitter in 12 kHz to 20 MHz band

tj_12k_20M

—

fsRMS

Note 1, Note 2

(100 MHz clock)

—

fsRMS

Note 1, Note 2

(133 MHz clock)

Noise Floor

— –165 –163

dBc/Hz Note 1, Note 2

(100 MHz clock)

— –165 –163

dBc/Hz Note 1, Note 2

(133 MHz clock)

Note 1: Measured into AC test load as per Figure 1-7.

2: Measured from differential crossing point to differential crossing point.

3: Measured with 50Ω termination in instrument without a test load.

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