SY75604B datasheet(12/26 Pages) MICROCHIP

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SY75602A/02B/603A/03B/604A/04B

DS20006508B-page 12



2021 Microchip Technology Inc. and its subsidiaries

4.0

FUNCTIONAL DESCRIPTION

The SY75602A/02B/603A/03B/604A/04B are PCIe

clock buffers with ultra-low additive jitter. They can be

used in all PCIe 1/2/3/4/5 common clock and SRIS

applications.

SY75602A/02B are the industry’s smallest

(1.4 mm x 1.6 mm VDFN) two output PCIe clock

buffers.

SY75603A/03B and SY75604A/04B are two and four

output PCIe clock buffers with glitch free per-output

enable/disable control hardware pins. Both devices are

packaged in 3 mm x 3 mm VQFN.

The devices have embedded low-dropout regulators

(LDO) for superior power noise supply rejection. They

support 1.8V, 2.5V, and 3.3V supplies with tolerance of

±10% which exceeds ±9% required by PCIe Card

Electro Mechanical Specification.

4.1

Clock Input

Please refer to the Functional Block Diagrams on how

to terminate different signals fed to the input of the

device.

Figure 4-1 and Figure 4-2 show how to terminate input

of the device in most common cases: Low Power HCSL

(LPHCSL), HCSL, and single-ended LVCMOS.

FIGURE 4-1:

Input Driven by LPHCSL

Driver.

FIGURE 4-2:

Input Driven by HCSL

Driver.

Figure 4-3 shows how to terminate a single-ended

output, such as LVCMOS. This example assumes 50Ω

transmission line which is the most common for single

ended CMOS signaling. Ideally, resistors R1 and R2

should be 100Ω each and RO + RS should be 50Ω so

that the transmission line is terminated at both ends

with characteristic impedance. If the driving strength of

the output driver is not sufficient to drive low

impedance, the value of series resistor RS should be

increased. This will reduce the voltage swing at the

input but this should be fine as long as the input voltage

swing requirement is not violated (0.3V). The source

resistors of RS = 270Ω could be used for standard

LVCMOS driver. This will provide 516 mV of voltage

swing for 3.3V LVCMOS driver with load current of

(3.3V/2) * (1/(270Ω + 50Ω)) = 5.16 mA.

For optimum performance both differential input pins

(_p and _n) need to be DC biased to the same voltage.

Hence, the ratio R1/R2 should be equal to the ratio

R3/R4.

FIGURE 4-3:

Input Driven from a

Single-Ended CMOS Output.

The differential input has hysteresis of 30 mV that

prevents outputs from randomly toggling when both p

and n inputs are at the same voltage level. For

example, when p and n inputs are held low as in the

case when the buffer is driven from an HCSL driver that

is disabled.

4.2

Clock Outputs

Differential outputs have embedded termination

resistors as shown in Figure 4-4. This provides

significant saving relative to traditional current based

HCSL outputs which require four resistors per

differential output.

FIGURE 4-4:

Terminating Differential

Outputs.

Embedded

termination

resistors

SY75602A/603A/604A are matched for 85Ω and

embedded

termination

resistors

SY75602B/603B/604B are matched for 100Ω

differential transmission line.

MCHP

Device

VDD

Push-Pull di eren al driver (LPHCSL)

MCHP

Device

VDD

HCSL

Output

Z0 = 50

MCHP

Device

VDD

0.1 μF

Ro + Rs = Z0

VDD

R1/R2 = R3/R4

VDD

0.1 μF

442

332

237

VDD

3.3V

2.5V

1.8V

10 k

1.27 k

1.78 k

2.61 k

di eren al

VDD

HCSL Inp ut

100

di eren al

VDD

HCSL Inp ut

SY75602A/03A/04A

SY75602B/03B/04B

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