MIC33050 datasheet(11/22 Pages) MICROCHIP

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DS20006120B-page 11

MIC33050

4.0

FUNCTIONAL DESCRIPTION

4.1

VIN

VIN provides power to the MOSFETs for the switch

mode regulator section and to the analog supply

circuitry. Due to the high switching speeds, it is

recommended that a 2.2 µF or greater capacitor be

placed close to VIN and the power ground (PGND) pin

for bypassing.

4.2

The enable pin, EN, controls the on and off state of the

device. A high logic on the enable pin activates the

regulator while a low logic deactivates it. MIC33050

features built-in soft-start circuitry that reduces in-rush

current and prevents the output voltage from

overshooting at start-up. Do not leave floating.

4.3

The pins at the switch node, SW, are connected directly

to the internal inductor. Due to the high-speed

switching on this pin, the switch node should be routed

away from sensitive nodes such as the CFF and FB

pins.

4.4

OUT

The OUT pin is for the output voltage following the

internal inductor of the device. Connect an output filter

capacitor equal to 2.2 µF or greater to this pin.

4.5

SNS

The sense pin, SNS, is needed to sense the output

voltage at the output filter capacitor. In order for the

control loop to monitor the output voltage accurately it

is good practice to sense the output voltage at the

positive side of the output filter capacitor where voltage

ripple is smallest.

4.6

CFF

The CFF pin is connected to the SNS pin of MIC33050

with a feed-forward capacitor of 560 pF. The CFF pin

itself is compared with the internal reference voltage

(VREF) of the device and provides the control path to

control the output. VREF is equal to 400 mV. The CFF

pin is sensitive to noise and should be place away from

the SW pin.

4.7

The feedback pin is provided for the adjustable output

version. An external resistor divider network is

connected from the output and is compared to the

internal 400 mV internal reference voltage within the

control loop.

The output voltage, of the circuit in Figure 4-1, may be

calculated via the equation below:

EQUATION 4-1:

FIGURE 4-1:

MIC33050-AYHL

Application Schematic.

4.8

PGND

Power ground (PGND) is the ground path for high

current. The current loop for the power ground should

be as small as possible and separate from the analog

ground (AGND) loop.

4.9

AGND

Signal ground (AGND) is the ground path for the

biasing and control circuitry. The current loop for the

signal ground should be separate from the PGND loop.

VOUT 0.4V 1 R1

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