MIC23451 datasheet(12/28 Pages) MICROCHIP

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MIC23451

DS20006662A-page 12



2022 Microchip Technology Inc. and its subsidiaries

4.0

FUNCTIONAL DESCRIPTION

4.1

PVIN

The input supply (PVIN) provides power to the internal

MOSFETs for the switch mode regulator. The VIN

operating range is 2.7V to 5.5V, so an input capacitor,

with a minimum voltage rating of 6.3V is

recommended. Because of the high di/dt switching

speeds, a minimum 2.2 µF or 4.7 µF recommended

bypass capacitor, placed close to PVIN and the power

ground (PGND) pin, is required. Refer to the PCB

Layout Recommendations section for details.

4.2

AVIN

The input supply (AVIN) provides power to the internal

control circuitry. Because the high di/dt switching

speeds on PVIN cause small voltage spikes, a 50Ω RC

filter and a minimum 100 nF decoupling capacitor,

placed close to the AVIN and signal ground (AGND)

pin, is required.

4.3

A logic high signal on the enable pin (EN) activates the

output voltage of the device. A logic low signal on the

enable pin deactivates the output and reduces supply

current to 0.01 µA. The MIC23451 features internal

soft-start circuitry that reduces inrush current and

prevents the output voltage from overshooting at

start-up. Do not leave the EN pin floating.

4.4

The switch (SW) connects directly to one end of the

inductor and provides the current path during switching

cycles. The other end of the inductor is connected to

the load, SNS pin, and output capacitor. Because of the

high-speed switching on this pin, the switch node

should be routed away from sensitive nodes.

4.5

SNS

The sense (SNS) pin is connected to the output of the

device to provide feedback to the control circuitry. The

SNS connection should be placed close to the output

capacitor. Refer to the PCB Layout Recommendations

section for more details.

4.6

AGND

The analog ground (AGND) is the ground path for the

biasing and control circuitry. The current loop for the

signal ground should be separate from the power

ground (PGND) loop. Refer to the PCB Layout

Recommendations section for more details.

4.7

PGND

The power ground pin is the ground path for the high

current in PWM mode. The current loop for the power

ground should be as short and wide as possible and

separate from the analog ground (AGND) loop as

applicable.

Refer

the

PCB

Layout

Recommendations section for more details.

4.8

The power good (PG) pin is an open-drain output that

indicates logic high when the output voltage is typically

above 90% of its steady state voltage. A pull-up resistor

of more than 5 kΩ should be connected from PG to

VOUT.

4.9

The feedback (FB) pin is the control input for

programming the output voltage. A resistor divider

network is connected to this pin from the output and is

compared to the internal 0.62V reference within the

regulation loop.

The output voltage can be programmed between 1V

and 3.3V using Equation 4-1:

EQUATION 4-1:

Table 4-1 shows example feedback resistor values.

TABLE 4-1:

FEEDBACK RESISTOR

VALUES

VOUT

1.2V

274 kΩ

294 kΩ

1.5V

316 kΩ

221 kΩ

1.8V

301 kΩ

158 kΩ

2.5V

324 kΩ

107 kΩ

3.3V

309 kΩ

71.5 kΩ

VOUT

VREF 1 R1

-------











Where:

R1 = The top, VOUT-connected resistor.

R2 = The bottom, AGND-connected resistor.

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