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MPC5643L Datasheet(PDF) 102 Page - NXP Semiconductors |
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MPC5643L Datasheet(HTML) 102 Page - NXP Semiconductors |
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102 / 136 page ![]() MPC5643L Microcontroller Data Sheet, Rev. 10 Electrical characteristics NXP Semiconductors 102 Figure 11. Pad output delay 3.19 Reset sequence This section shows the duration for different reset sequences. It describes the different reset sequences and it specifies the start conditions and the end indication for the reset sequences. 3.19.1 Reset sequence duration Table 31 specifies the minimum and the maximum reset sequence duration for the five different reset sequences described in Section 3.19.2, Reset sequence description. 3.19.2 Reset sequence description The figures in this section show the internal states of the chip during the five different reset sequences. The doted lines in the figures indicate the starting point and the end point for which the duration is specified in Table 31. The start point and end point Table 31. RESET sequences No. Symbol Parameter Conditions TReset Unit Min Typ Max1 1 The maximum value is applicable only if the reset sequence duration is not prolonged by an extended assertion of RESET by an external reset generator. 1TDRB CC Destructive Reset Sequence, BIST enabled 28 34 39 ms 2TDR CC Destructive Reset Sequence, BIST disabled — 500 4200 5000 μs 3TERLB CC External Reset Sequence Long, BIST enabled 28 32 37 ms 4TFRL CC Functional Reset Sequence Long — 35 150 400 μs 5TFRS CC Functional Reset Sequence Short — 1 4 10 μs VDDE/2 VOH VOL Rising Edge Output Delay Falling Edge Output Delay Pad Data Input Pad Output |
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