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AM625 Datasheet(PDF) 10 Page - Texas Instruments |
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AM625 Datasheet(HTML) 10 Page - Texas Instruments |
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10 / 235 page  Figure 6-2 shows the ball locations for the 441-ball flip chip ball grid array (FCBGA BGA) package to quickly locate signal names and ball grid numbering. This figure is used in conjunction with Section 6.2.1 through Table 6-74 (Pin Attributes table and all Signal Descriptions tables, including the Connectivity Requirements table). 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 AA Y W V U T R P N M L K J H G F E D C B A Not to scale VSS OLDI0_A0N OLDI0_A0P OLDI0_A4N OLDI0_A5P OLDI0_A5N OLDI0 _CLK1P OLDI0_A7N VSS OLDI0_A6N USB0_DM VSS CSI0 _RXCLKP CSI0 _RXCLKN VSS RGMII1 _RXC RGMII1 _RD2 RGMII1 _TD3 RGMII1 _TD1 RGMII2 _TD0 VSS MMC0_CLK MMC0_DAT4 VSS VSS OLDI0_A4P VSS OLDI0 _CLK1N OLDI0_A7P OLDI0_A6P USB0_DP VSS CSI0_RXP0 CSI0_RXN0 VSS RGMII1 _RD3 RGMII1 _RD1 RGMII1 _TD2 RGMII2 _TXC RGMII2 _RD2 RGMII2 _RD1 RGMII2_TX _CTL MMC0_DAT3 MMC0_DAT2 MMC0_DAT5 MMC0_DAT6 OLDI0_A3P OLDI0_A3N VSS USB1_DM USB1_DP VSS CSI0_RXP3 CSI0_RXN3 VSS RGMII1_RX _CTL RGMII1 _RD0 RGMII1 _TXC RGMII2 _TD2 RGMII2 _RD0 RGMII2_RX _CTL RGMII2 _RD3 VOUT0 _HSYNC MMC0_DAT1 MMC0_DAT0 MMC0_CMD MMC0_DAT7 OLDI0_A1N OLDI0_A1P OLDI0 _CLK0N OLDI0 _CLK0P USB1 _RCALIB USB0_VBUS VSS CSI0_RXP1 CSI0_RXN1 VSS RGMII1_TX _CTL RGMII2 _TD3 MDIO0_MDC RGMII2 _RXC VSS VOUT0 _DATA15 VOUT0 _DATA13 VDDS_DDR DDR0_DQ11 DDR0_DQ12 DDR0_DQ13 VSS OLDI0_A2P OLDI0_A2N VSS USB1_VBUS VSS CSI0_RXP2 CSI0_RXN2 VSS RGMII1 _TD0 RGMII2 _TD1 MDIO0 _MDIO VOUT0 _PCLK VOUT0 _DATA14 VOUT0 _DATA12 VOUT0 _DATA11 VOUT0 _DATA8 DDR0_DQS1 DDR0_DQ10 VSS DDR0_DQ14 DDR0_DQ15 VSS VSS USB0 _RCALIB VSS VSS CSI0 _RXRCALIB VSS RSVD5 RSVD6 VSS VOUT0 _VSYNC VOUT0_DE VOUT0 _DATA10 VOUT0 _DATA7 VOUT0 _DATA5 VOUT0 _DATA6 DDR0_DQS1 _n DDR0_DQ9 DDR0_DQ8 DDR0_DM1 VSS RSVD4 VSS VSS VDDA_1P8 _OLDI0 VDDA_3P3 _USB VDDA_1P8 _USB VDDA_1P8 _CSIRX0 CAP_VDDS2 VDDSHV2 VDDSHV2 VSS VOUT0 _DATA9 VOUT0 _DATA2 VOUT0 _DATA3 VOUT0 _DATA4 VOUT0 _DATA0 VSS DDR0_A8 VSS DDR0_A6 DDR0_A12 VSS VDDSHV4 VDD_CORE VDDA_1P8 _OLDI0 VSS VDDA_CORE _USB VDDA_CORE _CSIRX0 VSS VDDA_PLL1 VSS VSS GPMC0 _WAIT1 VOUT0 _DATA1 GPMC0 _AD14 GPMC0 _AD15 GPMC0 _WAIT0 DDR0 _ALERT_n DDR0_A7 DDR0_A10 DDR0_A9 DDR0_A13 VSS VDDSHV4 CAP_VDDS4 VDD_CORE VDDA_PLL0 VDD_CORE VSS VDD_CORE VSS VDDSHV3 VDDSHV3 GPMC0 _AD12 GPMC0 _AD11 GPMC0 _AD13 GPMC0_AD8 GPMC0_AD9 DDR0_ACT _n DDR0_PAR DDR0_A11 RSVD7 RSVD8 VSS VDDA _TEMP0 VDD_CORE VSS VDDR_CORE VSS VDD_CORE VDDR_CORE VDD_CORE CAP_VDDS3 VSS GPMC0 _AD10 VSS GPMC0_CLK GPMC0_AD7 GPMC0_AD4 VSS DDR0_BG1 DDR0_BA1 DDR0_BG0 DDR0_BA0 VSS VDDS_DDR _C VDDS_DDR VDDA_DDR _PLL0 VSS VDD_CORE VSS VDD_CORE VSS CAP_VDDS1 VSS GPMC0_AD5 GPMC0_AD6 GPMC0_AD1 GPMC0_AD2 GPMC0_AD3 DDR0_CK0 _n DDR0_ODT1 VSS DDR0_CAL0 DDR0_RAS _n VSS VDDS_DDR VSS VDDS_DDR VDD_CORE VMON_3P3 _SOC VDDA_PLL2 VSS VDD_CORE VDDSHV1 VDDSHV1 GPMC0 _BE0n_CLE GPMC0 _BE1n GPMC0_AD0 GPMC0 _ADVn_ALE GPMC0_OEn _REn DDR0_CK0 DDR0_WE_n DDR0_CAS _n DDR0_ODT0 DDR0_A4 VSS VDDS_OSC0 VDDS_DDR VDD_CORE VSS VDD_CORE VSS VDD_CORE VSS CAP_VDDS6 VSS GPMC0_WEn GPMC0 _CSn0 GPMC0_DIR GPMC0_WPn OSPI0_D7 VSS DDR0_CKE1 DDR0_CS0 _n DDR0_A3 DDR0_A5 VSS VDDSHV _CANUART VDD _CANUART VMON_1P8 _SOC VDDA_MCU VDDR_CORE VDD_CORE VSS VDD_CORE VDDSHV6 VDDSHV6 GPMC0 _CSn1 GPMC0 _CSn2 GPMC0 _CSn3 OSPI0_DQS OSPI0_D5 DDR0_CS1 _n DDR0 _RESET0_n DDR0_CKE0 DDR0_A2 DDR0_A1 VSS VDDSHV _CANUART CAP_VDDS _CANUART VSS VDDSHV _MCU CAP_VDDS _MCU CAP_VDDS0 VDDSHV0 VDDSHV5 CAP_VDDS5 VSS OSPI0_D1 OSPI0 _LBCLKO OSPI0_CLK OSPI0_D6 OSPI0_D4 DDR0_DQ6 DDR0_DQ7 DDR0_DQ5 VSS DDR0_A0 VMON_VSYS VPP RSVD3 VSS VDDSHV _MCU VSS VDDSHV0 VSS VDDSHV5 VSS VDDA _TEMP1 OSPI0 _CSn1 OSPI0_D0 OSPI0 _CSn0 OSPI0_D3 OSPI0_D2 DDR0_DQS0 _n VSS DDR0_DM0 DDR0_DQ1 DDR0_DQ3 RSVD2 MCU_SPI0 _CS0 MCU_SPI0 _D0 WKUP_I2C0 _SCL TDO UART0_TXD I2C0_SCL PORz_OUT RESETSTA z RESET _REQz USB1 _DRVVBUS OSPI0 _CSn2 OSPI0 _CSn3 MMC2_DAT2 MMC2_DAT3 MMC2_CLK DDR0_DQS0 DDR0_DQ4 DDR0_DQ2 VSS MCU_MCAN1 _TX MCU_MCAN1 _RX MCU_UART0 _RTSn MCU_SPI0 _D1 EMU0 TDI VSS SPI0_CLK SPI0_CS1 I2C0_SDA MCASP0 _AFSR MCASP0 _ACLKR USB0 _DRVVBUS MCASP0 _AXR0 VSS MMC2_SDCD MMC2_DAT1 VDDS_DDR DDR0_DQ0 RSVD1 MCU_MCAN0 _RX MCU_MCAN0 _TX WKUP _UART0 _TXD PMIC_LPM _EN0 MCU_SPI0 _CS1 MCU _RESETz TCK SPI0_CS0 SPI0_D0 UART0 _RTSn EXT _REFCLK1 MMC1_SDCD MCASP0 _AFSX MCASP0 _ACLKX MMC1_CMD MMC1_DAT3 MMC2_SDWP MMC2_CMD MCU _ERRORn MCU_PORz RSVD0 WKUP _UART0 _RTSn WKUP _UART0 _RXD MCU_UART0 _TXD MCU_SPI0 _CLK MCU_UART0 _CTSn MCU_I2C0 _SCL EMU1 TMS WKUP _CLKOUT0 MCAN0_TX UART0 _CTSn MMC1_SDWP EXTINTn MCASP0 _AXR2 MCASP0 _AXR3 MMC1_DAT1 MMC1_DAT2 MMC2_DAT0 VSS WKUP _LFOSC0 _XI WKUP _LFOSC0 _XO VSS MCU_OSC0 _XI MCU_OSC0 _XO WKUP _UART0 _CTSn MCU_UART0 _RXD WKUP_I2C0 _SDA MCU_I2C0 _SDA TRSTn MCU_RESETS TATz UART0_RXD SPI0_D1 MCAN0_RX I2C1_SDA I2C1_SCL MCASP0 _AXR1 MMC1_DAT0 MMC1_CLK VSS Figure 6-2. AMC FCBGA Package (Bottom View) AM625, AM623 SPRSP58 – JUNE 2022 www.ti.com 10 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: AM625 AM623 |
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