1 Features

• Stereo high-performance ADC:

– 2-channel analog microphones or line-in

• ADC line and microphone differential and single-

ended input performance:

– PCM1822 dynamic range:

• 117-dB, dynamic range enhancer enabled

• 111-dB, dynamic range enhancer disabled

– THD+N: –95 dB

• Hardware pin control configurations

• Linear-phase or low-latency filter selection

• Flexible audio serial data interface:

– Master or slave interface selection

– 32-bits, 2-channel TDM

• Automatic power-down upon loss of audio clocks

• Integrated high-performance audio PLL

• Single-supply operation: 3.3 V

• I/O-supply operation: 3.3 V or 1.8 V

• Power consumption for 3.3-V AVDD supply:

– 19.6 mW/channel at 16-kHz sample rate

– 21.3 mW/channel at 48-kHz sample rate

2 Applications

• Smart Speakers

• DVD recorders and players

• AV receivers

• Video conference systems

• IP network cameras

3 Description

audio analog-to-digital converter (ADC) that supports

simultaneous sampling of up to two analog channels.

The device supports single-ended and differential line

The device integrates a phase-locked loop (PLL),

a DC removal high-pass filter (HPF), and supports

sample rates up to 192 kHz. The device supports

selectable with the hardware pin level. Additionally,

the PCM1822 supports master and slave mode

selection for the audio bus interface operation. These

integrated high-performance features, along with the

ability to be powered from a single supply of 3.3

V, make the device an excellent choice for cost-

sensitive, space-constrained audio systems in far-field

microphone recording applications.

The PCM1822 is specified from –40°C to +125°C, and

is offered in a 20-pin WQFN package.

Device Information(1)

PART NUMBER

PACKAGE

BODY SIZE (NOM)

PCM1822

WQFN (20)

3.00 mm × 3.00 mm with

0.5-mm pitch

(1)

For all available packages, see the package option

addendum at the end of the data sheet.

ADC

Channel-1

Digital

Decimation

Filters

with High Pass

Filter (HPF)

Audio Serial

Interface

(TDM, I2S)

BCLK

FSYNC

SDOUT

IN1M

IN1P

IN2M

IN2P

ADC

Channel-2

Regulators, Current Bias

and Voltage Reference

Clock and Timing

Controller with

Integrated PLL

Simplified Block Diagram

PCM1822

SBASAK0 – DECEMBER 2020 – REVISED MAY 2022

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.