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ADC3544 Datasheet(PDF) 13 Page - Texas Instruments |
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ADC3544 Datasheet(HTML) 13 Page - Texas Instruments |
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13 / 86 page  6.10 Timing Requirements (continued) Typical values are over the operating free-air temperature range, at TA = 25°C, full temperature range is TMIN = –40°C to TMAX = 105°C, ADC sampling rate = 65 MSPS, 50% clock duty cycle, AVDD, IOVDD = 1.8 V, and –1-dBFS differential input, unless otherwise noted PARAMETER TEST CONDITIONS MIN NOM MAX UNIT Interface Timing - SDR CMOS tPD Propagation delay: sampling clock falling edge to DCLK rising edge 3 5 7 ns tCD DCLK rising edge to output data delay Fout = 10 MSPS -0.3 -0.2 ns DCLK rising edge to output data delay Fout = 25 MSPS -0.3 -0.2 DCLK rising edge to output data delay Fout = 65 MSPS -0.3 -0.2 tDV Data valid, SDR CMOS Fout = 10 MSPS 99.9 99.9 ns Data valid, SDR CMOS Fout = 25 MSPS 39.9 39.9 Data valid, SDR CMOS Fout = 65 MSPS 15.1 15.3 Interface Timing - DDR CMOS tPD Propagation delay: sampling clock falling edge to DCLK rising edge 3 5 7 ns tCD DCLK rising edge to output data delay Fout = 10 MSPS -0.3 -0.2 ns DCLK rising edge to output data delay Fout = 25 MSPS -0.4 -0.2 DCLK rising edge to output data delay Fout = 65 MSPS -0.4 -0.2 tDV Data valid, DDR CMOS Fout = 10 MSPS 49.5 49.9 ns Data valid, DDR CMOS Fout = 25 MSPS 19.6 19.8 Data valid, DDR CMOS Fout = 65 MSPS 7.4 7.5 Interface Timing - SERIAL CMOS tPD Propagation delay: sampling clock falling edge to DCLK rising edge Delay between sampling clock falling edge to DCLKIN falling edge < 2.5ns. TDCLK = DCLK period tCDCLK = Sampling clock falling edge to DCLKIN falling edge 2 + TDCLK + tCDCLK 3 + TDCLK + tCDCLK 4 + TDCLK + tCDCLK ns Delay between sampling clock falling edge to DCLKIN falling edge >= 2.5ns. TDCLK = DCLK period tCDCLK = Sampling clock falling edge to DCLKIN falling edge 2 + tCDCLK 3 + tCDCLK 4 + tCDCLK tCD DCLK rising edge to output data delay, 2-wire serial CMOS Fout = 10 MSPS, D11/12 = 70 MBPS 0.04 0.18 ns Fout = 25 MSPS, D11/12 = 175 MBPS 0.01 0.18 DCLK rising edge to output data delay, 1-wire serial CMOS Fout = 10 MSPS, D11 = 140 MBPS 0.05 0.19 tDV Data valid, 2-wire serial CMOS Fout = 10 MSPS, D11/12 = 70 MBPS 13.4 13.8 ns Fout = 25 MSPS, D11/12 = 175 MBPS 5.2 5.5 Data valid, 1-wire serial CMOS Fout = 10 MSPS, D11 = 140 MBPS 6.2 6.8 SERIAL PROGRAMMING INTERFACE (SCLK, SEN, SDIO) - Input fCLK(SCLK) Serial clock frequency 20 MHz tSU(SEN) SEN to rising edge of SCLK 10 ns tH(SEN) SEN from rising edge of SCLK 9 tSU(SDIO) SDIO to rising edge of SCLK 17 tH(SDIO) SDIO from rising edge of SCLK 9 SERIAL PROGRAMMING INTERFACE (SDIO) - Output t(OZD) SDIO tri-state to driven 3.9 10.8 ns t(ODZ) SDIO data to tri-state 3.4 14 t(OD) SDIO valid from falling edge of SCLK 3.9 10.8 www.ti.com ADC3541, ADC3542 SBAS840B – JULY 2020 – REVISED APRIL 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: ADC3541 ADC3542 |
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