Final datasheet

12

Rev.2.7

2021-09-10

EiceDRIVER™ 2EDi product family

2EDSx reinforced, 2EDFx functional isolated 4A/8A, 1A/2A gate drivers

Functional description

3.4

Input configurations

The inputs INA and INB control two independent PWM channels. The input signal is transferred non-inverted to

the corresponding gate driver outputs OUTA and OUTB. All inputs are compatible with LV-TTL threshold levels

and provide a hysteresis of typ. 0.8 V. The hysteresis is independent of the supply voltage VDDI.

The PWM inputs are internally pulled down to a logic low voltage level (GNDI). In case the PWM-controller signals

have an undefined state during the power-up sequence, the gate driver outputs are forced to the "off"-state

(low).

If the DISABLE input is “high”, this unconditionally drives both channel outputs to “low” regardless of the state of

INA or INB.

3.5

Driver outputs

The two rail-to-rail output stages, realized with complementary PMOS, NMOS transistors, are able to provide the

necessary sourcing and sinking current and shoot-through protection and active current limitation have been

implemented with a very low on-resistance (see Table 15). The use of a p-channel sourcing transistor PMOS is

crucial for achieving true rail-to-rail behavior without any source follower voltage drop.

Gate Drive Outputs OUTA, OUTB are held actively low in case of floating inputs or during startup or power down

as long as the UVLO thresholds are not exceeded.

Table 5

Logic table

Inputs

Gate Drive Output

DISABLE

INA

INB UVLO

1) “inactive” means that VDD is above UVLO threshold voltage (normal operation)

“active” means that UVLO disables the gate driver output stages

UVLO

OUTA

OUTB

xx

x

active

x

L

L

xx

x

x

ch A/B active

L

L

L

x

L

inactive

ch A activ, ch B inactive

L

L

L

x

H

inactive

ch A active, ch B inactive

L

H

L

L

x

inactive

ch A inactive, ch B active

L

L

L

H

x

inactive

ch A inactive, ch B active

H

L

Hx

x

inactive

ch A/B inactive

L

L

LL

L

inactive

ch A/B inactive

L

L

LL

H

inactive

ch A/B inactive

L

H

LH

H

inactive

ch A/B inactive

H

H