CC2500 datasheet(20/76 Pages) TI

20 / 76 page

CC2500

Preliminary Data Sheet (rev.1.1.)

SWRS040

Page 20 of 77

Read from register:

Write to register:

Hi-Z

SCLK:

CSn:

SO Hi-Z

Hi-Z

Figure 6: Configuration registers write and read operations (A6 is the “burst” bit)

Parameter

Description

Min

Max

Units

FSCLK

SCLK frequency

MHz

tsp,pd

CSn low to positive edge on SCLK, in power-down mode

TBD

µs

tsp

CSn low to positive edge on SCLK, in active mode

TBD

tch

Clock high

tcl

Clock low

trise

Clock rise time

TBD

tfall

Clock rise time

TBD

tsd

Setup data to positive edge on

SCLK

TBD

thd

Hold data after positive edge on

SCLK

TBD

tns

Negative edge on

SCLK to CSn high.

TBD

Table 16: SPI interface timing requirements

DATA

byte 0

ADDR

FIFO

DATA

byte 1 DATAbyte 2

DATA

byte n-1 DATAbyte n

...

ADDR

strobe

DATA

ADDR

strobe

ADDRreg

ADDRreg n

DATAn

DATAn+1

DATAn+2

...

ADDR

strobe

...

CSn:

Command strobe(s):

Read or write register(s):

Read or write consecutive registers (burst):

DATA

ADDRreg

DATA

ADDRreg

...

DATA

byte 0

ADDR

FIFO

DATA

byte 1

Combinations:

DATA

ADDR

reg

DATA

ADDR

reg

ADDR

strobe

ADDR

strobe

...

Read or write n+1 bytes from/to RF FIFO:

Figure 7: Register access types

10.1 Chip Status Byte

When the header byte, data byte or command

strobe is sent on the SPI interface, the chip

status byte is sent by the

CC2500 on the SO

pin. The status byte contains key status

signals, useful for the MCU. The first bit, s7, is

the CHIP_RDYn signal; this signal must go low

before the first positive edge of SCLK. The

CHIP_RDYn signal indicates that the crystal is

running and the regulated digital supply

voltage is stable.

CC2500 Datasheet(PDF) 20 Page - Texas Instruments

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