List of figures

Figure 1.

Block diagram .................................................................... 2

Figure 2.

Tone enable and disable timing (using external waveform) ...................................... 3

Figure 3.

Tone enable and disable timing (using envelope signal) ........................................ 4

Figure 4.

Surge protection circuit .............................................................. 5

Figure 5.

Pin connections (top view) ............................................................ 8

Figure 6.

DiSEqC 1.x application circuit ......................................................... 11

Figure 7.

DiSEqC 2.x application circuit ......................................................... 12

Figure 8.

Data validity on the I²C bus .......................................................... 15

Figure 9.

Timing diagram of I²C bus ........................................................... 15

Figure 10.

Acknowledge on the I²C bus.......................................................... 15

Figure 11.

Example of writing procedure starting with first data address 0x2 ................................ 16

Figure 12.

Example of reading procedure starting with first status address 0X0 .............................. 17

Figure 13.

QFN24 (4x4 mm) package outline ...................................................... 28

Figure 14.

QFN24 (4x4 mm) footprint recommended data ............................................. 29

LNBH26S

List of figures

DS8975 - Rev 5

page 34/35