AP65455

Document number: DS37994 Rev. 3 - 4

2 of 15

www.diodes.com

October 2018

© Diodes Incorporated

AP65455

PART OBSOLETE - NO ALTERNATE PART

Typical Applications Circuit

AP65455

L1

1.5

μH

R1

8.25k

Ω

R3

22.1k

Ω

C1

0.1

µF

C3

44

μF

C2

20

μF

C4

8.2n

F

ON

OFF

VIN

SS

EN

VREG5

SW

BST

FB

C5

1

µF

PGND

INPUT

OUTPUT

VOUT

1.05V

VIN

12V

PG

PGOOD

VREG5

R2

100k

Ω

Figure 1 Typical Application Circuit

Pin Descriptions

Pin

Name

Package

Function

U-DFN3030-10

EN

1

Enable Input. EN is a digital input that turns the regulator on or off. Drive EN high to turn on the

regulator, drive it low to turn off. EN can be safely connected to VIN directly for automatic startup.

FB

2

Feedback Input. FB senses the output voltage and regulates it. Drive FB with a resistive voltage

divider connected to it from the output voltage.

VREG5

3

Internal power supply output pin to connect an additional capacitor. Connect a

1μF (typical)

capacitor as close as possible to the VREG5 and PGND. This pin is not active when EN is low.

SS

4

Soft-start control input pin. SS controls the soft start period. Connect a capacitor from SS to PGND

to set the soft-start period.

SW

6,7

Power Switching Output. SW is the switching node that supplies power to the output. Connect the

output LC filter from SW to the output load. Note that a capacitor is required from SW to BST to

power the high-side switch.

BST

8

Bootstrap pin. A bootstrap capacitor is connected between the BST pin and SW pin. The voltage

across the bootstrap capacitor drives the internal high-

side NMOS switch. A 0.1μF (typical)

capacitor is required for proper operation.

VIN

9,10

Supply Input. A capacitor should be connected between the VIN pin and PGND pin to keep the

DC input voltage constant.

PG

5

Open drain power good output.

PGND

11 (Exposed

Pad)

Power ground and PGND. Exposed pad must be connected to PGND plane as large as possible

for maximum thermal performance.