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CL-GD6420 Datasheet(PDF) 66 Page - Cirrus Logic |
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CL-GD6420 Datasheet(HTML) 66 Page - Cirrus Logic |
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66 / 146 page  CL-GD6420 Notebook VGA Controller 66 July 1993 DATA BOOK 7.3.4 CPU Base Address Control Register: ER0D (cont.) Bit Description Bits 7:4 Reserved Bit 2 2/1 Page Selection: If Bit 2 is reset to a ‘0’, remapping is possible only through ER0E. If Bit 2 is set to a ‘1’, remapping is possible through both ER0E and ER0F. Bit 1 64K/32K Page Size: If Bit 1 is reset to a ‘0’, remapping is done for 32K pages. If Bit 1 is set to a ‘1’, remapping is done for 64K pages. The following table summa- rizes the remapping according to the CPU address. a. (*) indicates the address is not modified in the Remapping Logic. b. To use two pages of 64K each, program GR6[3:2] to 0:0; 128K of Display Memory is selected. Bit 0 Enable Page Remapping: If this bit is reset to a ‘0’, the address is passed through the Remapping Logic with no modification. Table 7–3. Remapping Register Selection Bit 2 Bit 1 A000- A7FFF A8000- AFFFF B0000- B7FFF B8000- BFFFF 0 0 ER0E * a ** 0 1 ER0E ER0E * * 1 0 ER0E ER0F * * 1 1 ER0E ER0E ER0F ER0Fb |
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