CL-GD6420 datasheet(13/146 Pages) CIRRUS

13 / 146 page

CL-GD6420

Notebook VGA Controller

July 1993

DATA BOOK

Several dedicated pins have been assigned to fa-

cilitate power management. The PWG Signal

(Power Good) can be used to signify the beginning

of a power-on or power-off sequence. The signal

FPVCC and FPVEE can be used to control panel

logic power and panel back light/contrast, when a

panel requires that these functions be sequenced

or controlled.

Normal Mode

• Power to LCD panel and full screen refresh

• CPU access to Video Memory

• Refresh to Video Memory

• CPU access to RAMDAC

• CPU access to I/O Registers

Since power consumption is directly proportional

to the frequency at which the controller is run, the

CL-GD6420 uses a proprietary Frame-Accelerator

to maintain the maximum screen refresh rate,

while the clock to the CL-GD6420 functions at 25

MHz or less. The Frame-Accelerator is used only

with dual-scan LCD panels.

Standby Mode

• No power to LCD panel and no screen refresh

• Panel power sequencing is observed

• CPU access to Video Memory

• Refresh to Video Memory

• CPU access to RAMDAC

• CPU access to I/O Registers

• Frequency Synthesizer is not powered-down

The primary power savings in this mode comes

from cutting power to the LCD panel only. Since

there is no screen refresh, normal clock rates are

not required and may be replaced by slower clock

rates to further reduce power consumption. The

SSCLK (Screen-Save-Clock) input pin can be

used to detect a variety of external system activi-

ties: detecting keyboard activity is one recom-

mended implementation. Any RAMDAC I/O can be

executed. The system will recover from Standby

Mode after receiving stimuli in the form of video

memory read or write accesses, or the presence of

the SSCLK Signal. If power sequencing is in

progress, then the CL-GD6420 will allow the se-

quencing to complete before exiting Standby

Mode.

The CL-GD6420 contains a power-save timer that

allows it to be programmable in increments of one

minute up to 63 minutes with an accuracy of

± 15

seconds. If the feature is enabled, this is the time-

out time from the last stimuli to automatically

switch to Standby Mode. The timer stimuli can be

by either the SSCLK Signal or by CPU memory ac-

cess (read or write). The input signal STANDBY*

can be used by external hardware to enter or exit

from this mode. Use of the STANDBY* Pin can be

combined with the software method in any combi-

nation.

Suspend Mode

• No power to LCD panel and no screen refresh

• Panel power sequencing is observed

• No CPU access to Video Memory

• Refresh to Video Memory continues but using

a 32 kHz clock

• No CPU access to RAMDAC

• No CPU access to I/O Registers

• Frequency Synthesizer is powered-down

The power savings in this mode occurs because

host access to video memory is now denied, and a

slower clock is used. This slow clock refreshes vid-

eo memory by performing CAS*-before-RAS* re-

fresh. With slow-refresh DRAM, a clock running as

slow as 32 kHz can be used. If calculations indi-

cate that 32 kHz violates the selected DRAM re-

fresh specifications, then the CL-GD6420 can pro-

vide 64 kHz from the 32 kHz input. Other than this

refresh logic, the rest of the CL-GD6420 does not

have clocks, reducing power consumption even

further.

Suspend Mode can be activated or deactivated,

under program control, by a sequence of three

consecutive I/O writes to the ‘active’ IBM VGA-

compatible ‘Sleep’ Port (46E8H or 3C3H).

Shutdown

• No power to LCD panel

• No clocks to the VGA controller subsystem

Prior to initiating a system-wide shutdown, the vid-

eo-subsystem state can be saved by the system it-

self for later restoration. The CL-GD6420 allows

the system to save or restore the status of all con-

troller registers.

CL-GD6420 Datasheet(PDF) 13 Page - Cirrus Logic

CL-GD6420 Datasheet(HTML) 13 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL