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CL-GD6420 Datasheet(PDF) 7 Page - Cirrus Logic |
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CL-GD6420 Datasheet(HTML) 7 Page - Cirrus Logic |
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7 / 146 page ![]() CL-GD6420 Notebook VGA Controller July 1993 7 DATA BOOK 2. Detailed Pin Description (cont.) Name Pin No. Type Description CLKPW* 140 O CLOCK CHIP POWER CONTROL: Active low, can be used to control external transistor logic connected to clock synthesizer power pins. This signal is active in Suspend Mode. RAS*[1:0] 142:141 O VIDEO MEMORY RAS*: RAS*[0] to AA Bus, RAS*[1] to AB CAS*[1:0] 144:143 Bus. CAS*[1:0] 143:144 O VIDEO MEMORY CAS*: CAS*[0] to AA Bus, CAS[*1] to AB Bus. M0D[7]/MID[2] 119 I/O VIDEO MEMORY DATA PIN: Planes 0 and 1, Bit 7. MONITOR ID BIT 2. The state of this pin is sampled at reset and latched into ER9C[7]. M0D[6]/MID[1] 120 I/O VIDEO MEMORY DATA PIN: Planes 0 and 1, Bit 6. MONITOR ID BIT 1. The state of this pin is sampled at reset and latched into ER9C[6]. M0D[5]/MID[0] 121 I/O VIDEO MEMORY DATA PIN: Planes 0 and 1, Bit 5. MONITOR ID BIT 0. The state of this pin is sampled at reset and latched into ER9C[5]. M0D[4:0] 126:122 I/O VIDEO MEMORY DATA PINS: Planes 0 and 1, Bits 4:0. M2D[7]/PD7 3 I/O VIDEO MEMORY DATA PINS: Planes 2 and 3, Bit 7. PULL DOWN # 7: The state of this pin is sampled at reset and latched into ER99[7]. M2D[6:0] 2, 1, I/O VIDEO MEMORY DATA PINS: Planes 2 and 3, Bits 6:0. 160:156 FRWE* 118 O FRAME-ACCELERATOR WRITE ENABLE*. FRCAS * 117 O FRAME-ACCELERATOR CAS*. FRRAS* 116 O FRAME-ACCELERATOR RAS*. FROE* 115 O FRAME-ACCELERATOR OE*. FRAD3/SW1 114 I/O FRAME-ACCELERATOR MULTIPLEXED ADDRESS/DA- TA[3] multiplexed with Switch 1. FRAD2/SW2 113 I/O FRAME-ACCELERATOR MULTIPLEXED ADDRESS/DA- TA[2] multiplexed with Switch 2. |
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