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TC387 Datasheet(PDF) 7 Page - Infineon Technologies AG

Part # TC387
Description  32-Bit Single-Chip Microcontroller
PDF  416 Pages
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Manufacturer  INFINEON [Infineon Technologies AG]
Direct Link  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

TC387 Datasheet(HTML) 7 Page - Infineon Technologies AG

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TC38x AD/AE-Step
Summary of Features
Data Sheet
7
V 1.2, 2021-03
1
Summary of Features
The TC38x product family has the following features:
•
High Performance Microcontroller with four CPU cores
•
Four 32-bit super-scalar TriCore CPUs (TC1.6.2P), each having the following features:
– Superior real-time performance
– Strong bit handling
– Fully integrated DSP capabilities
– Multiply-accumulate unit able to sustain 2 MAC operations per cycle
– Fully pipelined Floating point unit (FPU)
– up to 300 MHz operation at full temperature range
– up to 240/96 Kbyte Data Scratch-Pad RAM (DSPR)
– up to 64 Kbyte Instruction Scratch-Pad RAM (PSPR)
– up to 64 Kbyte Data RAM (DLMU)
– 32 Kbyte Instruction Cache (ICACHE)
– 16 Kbyte Data Cache (DCACHE)
•
Lockstepped shadow cores for two TC1.6.2P
•
Multiple on-chip memories
– All embedded NVM and SRAM are ECC protected
– up to 10 Mbyte Program Flash Memory (PFLASH)
– up to 512 Kbyte Data Flash Memory (DFLASH 0) usable for EEPROM emulation
– 128 Kbyte Memory (LMU)
– BootROM (BROM)
•
128-Channel DMA Controller with safe data transfer
•
Sophisticated interrupt system (ECC protected)
•
High performance on-chip bus structure
– 64-bit Cross Bar Interconnect (SRI) giving fast parallel access between bus masters, CPUs and memories
– 32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units
– SRI to SPB bus bridges (SFI Bridge)
•
Optional Hardware Security Module (HSM) on some variants
•
Safety Management Unit (SMU) handling safety monitor alarms
•
Memory Test Unit with ECC, Memory Initialization and MBIST functions (MTU)
•
Hardware I/O Monitor (IOM) for checking of digital I/O
•
Versatile On-chip Peripheral Units
– 24 Asynchronous/Synchronous Serial Channels (ASCLIN) with hardware LIN support (V1.3, V2.0, V2.1
and J2602) up to 50 MBaud
– 5 Queued SPI Interface Channels (QSPI) with master and slave capability up to 50 Mbit/s
– 1 High Speed Serial Link (HSSL) for serial inter-processor communication up to 320 Mbit/s
– 3 serial Micro Second Bus interfaces (MSC) for serial port expansion to external power devices
– 3 MCMCAN Modules with 4 CAN nodes for high efficiency data handling via FIFO buffering
– 25 Single Edge Nibble Transmission (SENT) channels for connection to sensors
–2 FlexRayTM module with 2 channels (E-Ray) supporting V2.1
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