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TC387 Datasheet(PDF) 143 Page - Infineon Technologies AG |
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TC387 Datasheet(HTML) 143 Page - Infineon Technologies AG |
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143 / 416 page ![]() TC38x AD/AE-Step Pin Definition and Functions BGA516 Package Variant Pin Configuration Data Sheet 143 V 1.2, 2021-03 AD20 P33.10 I FAST / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM4_IN4_14 Mux input channel 4 of TIM module 4 GTM_TIM1_IN0_9 Mux input channel 0 of TIM module 1 GTM_TIM0_IN0_9 Mux input channel 0 of TIM module 0 QSPI4_SLSIA Slave select input CAN01_RXDD CAN receive input node 1 ASCLIN0_ARXD Receive input IOM_PIN_10 GPIO pad input to FPC P33.10 O0 General-purpose output GTM_TOUT32 O1 GTM muxed output IOM_MON0_10 Monitor input 0 QSPI1_SLSO6 O2 Master slave select output QSPI4_SLSO0 O3 Master slave select output ASCLIN1_ASLSO O4 Slave select signal output PSI5S_CLK O5 PSI5S CLK is a clock that can be used on a pin to drive the external PHY. —O6 Reserved CCU61_COUT61 O7 T12 PWM channel 61 IOM_MON1_12 Monitor input 1 IOM_REF1_9 Reference input 1 SMU_FSP1 O FSP[1..0] Output Signals - Generated by SMU_core AE20 P33.11 I FAST / PU1 / VEVRSB / ES5 General-purpose input GTM_TIM1_IN2_8 Mux input channel 2 of TIM module 1 GTM_TIM0_IN2_8 Mux input channel 2 of TIM module 0 QSPI4_SCLKA Slave SPI clock inputs IOM_PIN_11 GPIO pad input to FPC P33.11 O0 General-purpose output GTM_TOUT33 O1 GTM muxed output IOM_MON0_11 Monitor input 0 ASCLIN1_ASCLK O2 Shift clock output QSPI4_SCLK O3 Master SPI clock output —O4 Reserved —O5 Reserved EDSADC_CGPWMN O6 Negative carrier generator output CCU61_CC61 O7 T12 PWM channel 61 IOM_MON1_9 Monitor input 1 IOM_REF1_12 Reference input 1 Table 2-20 Port 33 Functions (cont’d) Ball Symbol Ctrl. Buffer Type Function OPEN MARKET VERSION |
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