LM5032 datasheet(12/22 Pages) NSC

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Oscillator (Continued)

age at the R

T/SYNC pin is internally regulated at 2.0V. The

T resistor should be located as close as possible to the

LM5032 with short direct connections to the pins.

The LM5032 can be synchronized to an external clock by

applying a narrow clock pulse to the R

T/SYNC pin. See the

Applications Information section for details on this proce-

dure. The R

T resistor is always required, whether the oscil-

lator is free running or externally synchronized.

PWM Comparator/Slope

Compensation

The PWM comparator of each controller compares a slope

compensated current ramp signal with the loop error voltage

derived from the COMP pin. The COMP voltage is typically

controlled by an external error amplifier/optocoupler feed-

back circuit to regulate the converter output voltage. Inter-

nally, the voltage at the COMP pin passes through two level

shifting diodes and a gain reducing 3:1 resistor divider (see

Figure 16). The compensated current ramp signal is a com-

bination of the current waveform at the CS pin, and an

internally generated ramp derived from the internal clock. At

duty cycles greater than 50% current mode control circuits

are prone to subharmonic oscillation. By adding a small fixed

ramp to the external current sense signal oscillations can be

avoided. The internal ramp has an amplitude of 45 µA and is

sourced into an internal 2k

Ω resistor, and a 42 kΩ resistor in

parallel with the external impedance at the CS pin. The ramp

current also flows through the external impedance con-

nected to the CS pin and thus, the amount of slope compen-

sation can be adjusted by varying the external circuit at the

CS pin.

The output of the PWM comparator provides the pulse width

information to the output drivers. This comparator is opti-

mized for speed in order to achieve minimum controllable

duty cycles. The comparator’s output duty cycle is 0% for

COMP

≤1.5V, and increases as V

COMP increases.

If either Soft-start pin is pulled low (internally or externally)

the corresponding COMP pin is pulled down with it, forcing

the output duty cycle to zero. When the Soft-start pin voltage

increases, the COMP pin is allowed to increase. An internal

Ω resistor connected from COMP to an internal 5.0V

supply provides a pull-up for the COMP pin and bias current

to the collector of the opto-coupler transistor.

Cycle-by-Cycle Current Limit

Each CS pin is designed to accept a signal representative of

its transformer primary current. If the voltage at CS exceeds

0.5V the current sense comparator terminates the present

main output driver (OUT pin) pulse. If the high current fault

persists, the controller operates with constant peak switch

current in a cycle-by-cycle current limit mode, and a Hiccup

Mode Current Limit Restart cycle begins (see below).

Each CS pin is internally connect to ground through a 30

Ω

resistor during the main output off time to discharge external

filter capacitance. The discharge device remains on for an

additional 50 ns after the main output driver switches high to

blank leading edge transients in the current sensing circuit.

Discharging the CS pin filter each cycle and blanking leading

edge spikes reduces the filter requirement which improves

the current sense response time.

The current sense comparators are fast and respond to short

duration noise pulses. The external circuitry at each CS pin

should include an R-C filter to suppress noise. Layout con-

siderations are critical for the current sense filter and the

sense resistor. Refer to the Applications Information section

for PC board layout guidelines.

Hiccup Mode Current Limit Restart

If cycle-by-cycle current limiting continues in either or both

controllers for a sufficient period of time, the Current Limit

Restart circuit disables both regulators and initiates a soft-

start sequence after a programmable delay. The duration of

cycle-by-cycle current limiting before turn-off occurs is pro-

grammed by the value of the external capacitor at the RES

pin. The dwell time before output switching resumes is pro-

grammed by the value of the Soft-start capacitor(s). The

circuit is detailed in Figure 17 and the timing is shown in

Figure 18. A description of this circuit’s operation is as fol-

lows:

a) No current limit detected:

20135022

FIGURE 16. Typical Feedback Network

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