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MPC8540 Datasheet(PDF) 223 Page - Freescale Semiconductor, Inc |
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MPC8540 Datasheet(HTML) 223 Page - Freescale Semiconductor, Inc |
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223 / 1302 page ![]() Features MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1 Freescale Semiconductor 5-9 Figure 5-3. Three-Stage Load/Store Unit The LSU has the following features: — 3-cycle load latency — Fully pipelined — The load miss queue allows up to four load misses before stalling. — Load hits can continue to be serviced when the load miss queue is full. — Seven-entry L1 store queue allows full pipelining of stores — The three-entry data line fill buffer is used for loads and cacheable stores. Stores are allocated here so loads can access data from the store immediately. — The data write buffer contains three entries: one dedicated for snoop pushes, one dedicated for cast outs, and one that can be used for snoop pushes or cast outs. • Cache coherency — Supports four-state cache coherency: modified-exclusive, exclusive, shared, and invalid (MESI) — Bus support for hardware-enforced coherency (bus snooping) • Core complex bus (CCB)—internal bus — High-speed, on-chip local bus with data tagging — 32-bit address bus — Address protocol with address pipelining and retry/copyback derived from bus used by previous generations of PowerPC processors (referred to as the 60x bus) — Two general-purpose read data buses and one write data bus Reservation Station Load/Store Unit (64-/32-Bit) Load Data Line Fill Buffer Data Write Buffer L1 Store Queue Miss Queue To Core Interface Unit To data cache To GPR operand bus To completion queue To GPRs Three-Stage Pipeline Queues and Buffers |
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