MPC8540 datasheet(50/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

Figures

Figure

Number

Title

Page

Number

13-42

SDRAM Single-Beat Read, Page Hit, CL = 3 .................................................................... 13-58

13-43

SDRAM Two-Beat Burst Read, Page Closed, CL = 3........................................................ 13-58

13-44

SDRAM Four-Beat Burst Read, Page Miss, CL = 3........................................................... 13-59

13-45

SDRAM Single-Beat Write, Page Hit................................................................................. 13-59

13-46

SDRAM Three-Beat Write, Page Closed............................................................................ 13-59

13-47

SDRAM Read-after-Read Pipelined, Page Hit, CL = 3...................................................... 13-59

13-48

SDRAM Write-after-Write Pipelined, Page Hit.................................................................. 13-60

13-49

SDRAM Read-after-Write Pipelined, Page Hit .................................................................. 13-60

13-50

SDRAM MODE-SET Command........................................................................................ 13-61

13-51

SDRAM Bank-Staggered Auto-Refresh Timing ................................................................ 13-62

13-52

User-Programmable Machine Functional Block Diagram.................................................. 13-62

13-53

RAM Array Indexing .......................................................................................................... 13-64

13-54

Memory Refresh Timer Request Block Diagram ............................................................... 13-65

13-55

UPM Clock Scheme for LCRR[CLKDIV] = 2................................................................... 13-67

13-56

UPM Clock Scheme for LCRR[CLKDIV] = 4 or 8 ........................................................... 13-67

13-57

RAM Array and Signal Generation .................................................................................... 13-68

13-58

RAM Word Field Descriptions ........................................................................................... 13-68

13-59

LCSn Signal Selection ........................................................................................................ 13-72

13-60

LBS Signal Selection .......................................................................................................... 13-73

13-61

UPM Read Access Data Sampling...................................................................................... 13-76

13-62

Effect of LUPWAIT Signal ................................................................................................. 13-77

13-63

Single-Beat Read Access to FPM DRAM .......................................................................... 13-79

13-64

Single-Beat Write Access to FPM DRAM ......................................................................... 13-80

13-65

Burst Read Access to FPM DRAM Using LOOP (Two Beats Shown).............................. 13-81

13-66

Refresh Cycle (CBR) to FPM DRAM ................................................................................ 13-82

13-67

Exception Cycle .................................................................................................................. 13-83

13-68

Multiplexed Address/Data Bus ........................................................................................... 13-84

13-69

Local Bus Peripheral Hierarchy .......................................................................................... 13-85

13-70

Local Bus Peripheral Hierarchy for Very High Bus Speeds ............................................... 13-86

13-71

GPCM Address Timings ..................................................................................................... 13-86

13-72

GPCM Data timings ............................................................................................................ 13-87

13-73

Interface to Different Port-Size Devices ............................................................................. 13-89

13-74

128-Mbyte SDRAM Diagram............................................................................................. 13-93

13-75

SDRAM Power-Down Timing............................................................................................ 13-97

13-76

SDRAM Self-Refresh Mode Timing .................................................................................. 13-98

13-77

Local Bus DLL Operation................................................................................................. 13-100

13-78

Parity Support for SDRAM............................................................................................... 13-101

13-79

Interface to ZBT SRAM ................................................................................................... 13-102

13-80

MSC8101 HDI16 Peripheral Registers ............................................................................. 13-104

13-81

Interface to MSC8101 HDI16........................................................................................... 13-105

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