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MPC8540 Datasheet(PDF) 32 Page - Freescale Semiconductor, Inc

Part # MPC8540
Description  MPC8540 PowerQUICC III??Integrated Host Processor Reference Manual
PDF  1302 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC8540 Datasheet(HTML) 32 Page - Freescale Semiconductor, Inc

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1
xxxii
Freescale Semiconductor
Contents
Paragraph
Number
Title
Page
Number
16.5.4
PCI-X Inbound Reads that Cross Window Boundaries ......................................... 16-101
16.5.5
Bridging Between RapidIO and PCI/X ................................................................. 16-101
Chapter 17
RapidIO Interface
17.1
Introduction.................................................................................................................... 17-1
17.1.1
Overview.................................................................................................................... 17-1
17.1.2
RapidIO Terminology ................................................................................................ 17-4
17.1.3
RapidIO Interface Features ........................................................................................ 17-4
17.1.3.1
Supported Features ................................................................................................ 17-4
17.1.3.2
Features Not Implemented..................................................................................... 17-5
17.1.4
RapidIO Modes of Operation .................................................................................... 17-5
17.1.4.1
Transmit Clock-Select Mode ................................................................................. 17-5
17.1.4.2
CRC Checking Modes ........................................................................................... 17-5
17.1.4.3
Error Checking Disable Mode ............................................................................... 17-6
17.1.4.4
Output Port Enable Mode ...................................................................................... 17-6
17.1.4.5
Output Port Driver Disable Mode.......................................................................... 17-6
17.1.4.6
Accept All Mode.................................................................................................... 17-6
17.1.4.7
Packet Response Time-Out Disable Mode ............................................................ 17-6
17.1.4.8
Link Response Time-Out Disable Mode ............................................................... 17-6
17.2
External Signal Descriptions ......................................................................................... 17-7
17.2.1
Signals Overview ....................................................................................................... 17-7
17.2.2
Detailed Signal Descriptions ..................................................................................... 17-8
17.3
Memory Map/Register Definition ................................................................................. 17-9
17.3.1
Architectural Registers ............................................................................................ 17-13
17.3.1.1
Device Identity Capability Register (DIDCAR).................................................. 17-13
17.3.1.2
Device Information Capability Register (DICAR).............................................. 17-14
17.3.1.3
Assembly Identity Capability Register (AIDCAR) ............................................. 17-14
17.3.1.4
Assembly Information Capability Register (AICAR) ......................................... 17-15
17.3.1.5
Processing Element Features Capability Register (PEFCAR) ............................ 17-15
17.3.1.6
Switch Port Information Capability Register (SPICAR)..................................... 17-17
17.3.1.7
Source Operations Capability Register (SOCAR)............................................... 17-17
17.3.1.8
Destination Operations Capability Register (DOCAR)....................................... 17-19
17.3.1.9
Mailbox Command and Status Register (MSR) .................................................. 17-22
17.3.1.10
Port-Write and Doorbell Command and Status Register (PWDCSR)................. 17-22
17.3.1.11
Processing Element Logic Layer Control Command and Status
Register (PELLCCSR) .................................................................................... 17-24
17.3.1.12
Local Configuration Space Base Address 1 Command and Status
Register (LCSBA1CSR).................................................................................. 17-24



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