MPC8540 datasheet(64/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

lxiv

Freescale Semiconductor

Tables

Table

Number

Title

Page

Number

4-25

Memory Debug Configuration.............................................................................................. 4-21

4-26

DDR Debug Configuration ................................................................................................... 4-21

4-27

PCI Output Hold Configuration (cfg_pci_mode = 1) ........................................................... 4-22

4-28

PCI-X Output Hold Configuration (cfg_pci_mode = 0) ....................................................... 4-22

4-29

Local Bus Output Hold Configuration.................................................................................. 4-22

4-30

General-Purpose POR Configuration.................................................................................... 4-23

5-1

Revision Level-to-Device Marking Cross-Reference ............................................................. 5-5

5-2

Performance Monitor APU Instructions ............................................................................... 5-12

5-3

Cache Block Lock and Unlock APU Instructions ................................................................ 5-12

5-4

Scalar and Vector Embedded Floating-Point APU Instructions ........................................... 5-13

5-5

BTB Locking APU Instructions............................................................................................ 5-13

5-6

Interrupt Registers................................................................................................................. 5-22

5-7

Interrupt Vector Registers and Exception Conditions ........................................................... 5-24

5-8

Differences Between the e500 Core and the PowerQUICC III Core Implementation ......... 5-33

6-1

Book E Special-Purpose Registers (by SPR Abbreviation).................................................... 6-4

6-2

Implementation-Specific SPRs (by SPR Abbreviation) ......................................................... 6-6

6-3

XER Field Description............................................................................................................ 6-9

6-4

BI Operand Settings for CR Fields ......................................................................................... 6-9

6-5

CR0 Bit Descriptions ............................................................................................................ 6-11

6-6

MSR Field Descriptions........................................................................................................ 6-12

6-7

PVR Field Descriptions ........................................................................................................ 6-14

6-8

TCR Field Descriptions ........................................................................................................ 6-15

6-9

TSR Field Descriptions ......................................................................................................... 6-16

6-10

IVOR Assignments ............................................................................................................... 6-20

6-11

ESR Field Descriptions ......................................................................................................... 6-21

6-12

MCSR Field Descriptions .....................................................................................................6-23

6-13

BBEAR Field Descriptions ................................................................................................... 6-25

6-14

BBTAR Field Descriptions ................................................................................................... 6-25

6-15

BUCSR Field Descriptions ................................................................................................... 6-26

6-16

HID0 Field Descriptions ....................................................................................................... 6-27

6-17

HID1 Field Descriptions ....................................................................................................... 6-28

6-18

L1CSR0 Field Descriptions .................................................................................................. 6-30

6-19

L1CSR1 Field Descriptions .................................................................................................. 6-31

6-20

L1CFG0 Field Descriptions .................................................................................................. 6-32

6-21

L1CFG1 Field Descriptions .................................................................................................. 6-33

6-22

MMUCSR0 Field Descriptions............................................................................................. 6-34

6-23

MMUCFG Field Descriptions .............................................................................................. 6-35

6-24

TLB0CFG Field Descriptions ............................................................................................... 6-36

6-25

TLB1CFG Field Descriptions ............................................................................................... 6-36

6-26

MAS0 Field Descriptions—MMU Read/Write and Replacement Control .......................... 6-37

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