MPC8540 datasheet(20/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

Contents

Paragraph

Number

Title

Page

Number

13.3.1.11

Transfer Error Check Disable Register (LTEDR)................................................ 13-27

13.3.1.12

Transfer Error Interrupt Enable Register (LTEIR) .............................................. 13-28

13.3.1.13

Transfer Error Attributes Register (LTEATR) ..................................................... 13-29

13.3.1.14

Transfer Error Address Register (LTEAR).......................................................... 13-30

13.3.1.15

Local Bus Configuration Register (LBCR) ......................................................... 13-31

13.3.1.16

Clock Ratio Register (LCRR).............................................................................. 13-32

13.4

Functional Description................................................................................................. 13-33

13.4.1

Basic Architecture.................................................................................................... 13-34

13.4.1.1

Address and Address Space Checking ................................................................ 13-34

13.4.1.2

External Address Latch Enable Signal (LALE) .................................................. 13-35

13.4.1.3

Data Transfer Acknowledge (TA) ....................................................................... 13-36

13.4.1.4

Data Buffer Control (LBCTL)............................................................................. 13-37

13.4.1.5

Atomic Operation ................................................................................................ 13-37

13.4.1.6

Parity Generation and Checking (LDP)............................................................... 13-38

13.4.1.7

Bus Monitor ......................................................................................................... 13-38

13.4.2

General-Purpose Chip-Select Machine (GPCM)..................................................... 13-38

13.4.2.1

Timing Configuration .......................................................................................... 13-39

13.4.2.2

Chip-Select Assertion Timing ............................................................................. 13-44

13.4.2.2.1

Programmable Wait State Configuration......................................................... 13-44

13.4.2.2.2

Chip-Select and Write Enable Negation Timing ............................................. 13-44

13.4.2.2.3

Relaxed Timing ............................................................................................... 13-45

13.4.2.2.4

Output Enable (LOE) Timing .......................................................................... 13-48

13.4.2.2.5

Extended Hold Time on Read Accesses .......................................................... 13-48

13.4.2.3

External Access Termination (LGTA) ................................................................. 13-49

13.4.2.4

Boot Chip-Select Operation................................................................................. 13-50

13.4.3

SDRAM Machine .................................................................................................... 13-51

13.4.3.1

Supported SDRAM Configurations..................................................................... 13-51

13.4.3.2

SDRAM Power-On Initialization ........................................................................ 13-52

13.4.3.3

Intel PC133 and JEDEC-Standard SDRAM Interface Commands ..................... 13-52

13.4.3.4

Page Hit Checking ............................................................................................... 13-53

13.4.3.5

Page Management................................................................................................ 13-54

13.4.3.6

SDRAM Address Multiplexing ........................................................................... 13-54

13.4.3.7

SDRAM Device-Specific Parameters.................................................................. 13-55

13.4.3.7.1

Precharge-to-Activate Interval......................................................................... 13-55

13.4.3.7.2

Activate-to-Read/Write Interval ...................................................................... 13-56

13.4.3.7.3

Column Address to First Data Out—CAS Latency......................................... 13-56

13.4.3.7.4

Last Data In to Precharge—Write Recovery ................................................... 13-56

13.4.3.7.5

Refresh Recovery Interval (RFRC) ................................................................. 13-57

13.4.3.7.6

External Address and Command Buffers (BUFCMD).................................... 13-57

13.4.3.8

SDRAM Interface Timing ................................................................................... 13-58

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