MPC8540 datasheet(238/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

5-24

Freescale Semiconductor

Core Complex Overview

5.9

Memory Management

The e500 core complex supports demand-paged virtual memory as well other memory

management schemes that depend on precise control of effective-to-physical address translation

and flexible memory protection as defined by Book E. The mapping mechanism consists of

software-managed TLBs that support variable-sized pages with per-page properties and

permissions. The following properties can be configured for each TLB:

•

User mode page execute access

•

User mode page read access

•

User mode page write access

•

Supervisor mode page execute access

Table 5-7. Interrupt Vector Registers and Exception Conditions

Interrupt

Book E–Defined IVORs

IVOR0

Critical input

IVOR1

Machine check interrupt offset

IVOR2

Data storage interrupt offset

IVOR3

Instruction storage interrupt offset

IVOR4

External input interrupt offset

IVOR5

Alignment interrupt offset

IVOR6

Program interrupt offset

IVOR7

Floating-point unavailable interrupt offset

IVOR8

System call interrupt offset

IVOR9

Auxiliary processor unavailable interrupt offset

IVOR10

Decrementer interrupt offset

IVOR11

Fixed-interval timer interrupt offset

IVOR12

Watchdog timer interrupt offset

IVOR13

Data TLB error interrupt offset

IVOR14

Instruction TLB error interrupt offset

IVOR15

Debug interrupt offset

e500-Specific IVORs

IVOR32

SPE APU unavailable interrupt offset

IVOR33

SPE floating-point data exception interrupt offset

IVOR34

SPE floating-point round exception interrupt offset

IVOR35

Performance monitor

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