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Branch Target Buffer (BTB) Registers

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

6-25

6.9

Branch Target Buffer (BTB) Registers

6.9.1

Branch Buffer Entry Address Register (BBEAR)

6.9.2

Branch Buffer Target Address Register (BBTAR)

Field

Branch buffer entry address

IAB[0–1]

Reset

All zeros

R/W

SPR

SPR 513

Figure 6-28. Branch Buffer Entry Address Register (BBEAR)

Table 6-13. BBEAR Field Descriptions

Bits

Name

Description

32–61

Branch buffer

entry address

Branch buffer entry effective address bits 0–29

62–63

IAB[0–1]

Instruction after branch (with BBTAR[62]). 3-bit pointer that points to the instruction in the

cache line after the branch. See the description in the bblels instruction in the EREF. If the

branch is the last instruction in the cache block, IAB = 000, to indicate the next sequential

instruction, which resides in the zeroth position of the next cache block.

Field

Branch buffer target address

IAB2 BDIRPR

Reset

All zeros

R/W

SPR

SPR 514

Figure 6-29. Branch Buffer Target Address Register (BBTAR)

Table 6-14. BBTAR Field Descriptions

Bits

Name

Description

32–61

Branch

buffer target

address

Branch buffer target effective address bits 0–29

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