MPC8540 datasheet(292/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

6-42

Freescale Semiconductor

Core Register Summary

6.13 Debug Registers

6.13.1 Debug Control Registers (DBCR0–DBCR2)

6.13.1.1 Debug Control Register 0 (DBCR0)

34 35

44 45 46 47

62 63

Field — IDM RST ICMP BRT IRPT TRAP IAC1 IAC2

—

DAC1 DAC2 RET

—

Reset

All zeros

R/W

SPR

SPR 308

Figure 6-48. Debug Control Register 0 (DBCR0)

Table 6-32. DBCR0 Field Descriptions

Bits

Name

Description

—

Reserved, should be cleared.

IDM

Internal debug mode

0 Debug interrupts are disabled. No debug interrupts are taken and debug events are not logged.

1 If MSR[DE] = 1, the occurrence of a debug event or the recording of an earlier debug event in

the DBSR when MSR[DE] = 0 or DBCR0[IDM] = 0 causes a debug interrupt.

Programming note: Software must clear debug event status in the DBSR in the debug interrupt

handler when a debug interrupt is taken before re-enabling interrupts through MSR[DE]. Otherwise,

redundant debug interrupts are taken for the same debug event.

34–35

RST

Reset. Book E defines this field such that 00 is always no action and all other settings are

implementation specific. The e500 implements these bits as follows:

0x Default (No action)

1x Causes a hard reset if MSR[DE] and DBCR0[IDM] are set. Always cleared on subsequent cycle.

ICMP

Instruction completion debug event enable

0 ICMP debug events are disabled

1 ICMP debug events are enabled

Note: Instruction completion does not cause an ICMP debug event if MSR[DE] = 0.

BRT

Branch taken debug event enable

0 BRT debug events are disabled

1 BRT debug events are enabled

Note: Taken branches do not cause a BRT debug event if MSR[DE] = 0.

IRPT

Interrupt taken debug event enable. This bit affects only noncritical interrupts.

0 IRPT debug events are disabled

1 IRPT debug events are enabled

TRAP

Trap debug event enable

0 TRAP debug events cannot occur

1 TRAP debug events can occur

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