MPC8540 datasheet(297/1302 Pages) FREESCALE

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Debug Registers

MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

6-47

6.13.3 Instruction Address Compare Registers (IAC1–IAC2)

BRT

Branch taken debug event. Set if a branch taken debug event occurred (DBCR0[BRT] = 1).

Functions as write-one-to-clear.

IRPT

Interrupt taken debug event. Set if an interrupt taken debug event occurred (DBCR0[IRPT] = 1).

Functions as write-one-to-clear.

TRAP

Trap instruction debug event. Set if a trap Instruction debug event occurred (DBCR0[TRAP] = 1).

Functions as write-one-to-clear.

IAC1

Instruction address compare 1 debug event. Set if an IAC1 debug event occurred

(DBCR0[IAC1] = 1). Functions as write-one-to-clear.

IAC2

Instruction address compare 2 debug event. Set if an IAC2 debug event occurred

(DBCR0[IAC2] = 1). Functions as write-one-to-clear.

42–43

—

Reserved, should be cleared

DAC1R Data address compare 1 read debug event. Set if a read-type DAC1 debug event occurred

(DBCR0[DAC1] = 10 or 11). Functions as write-one-to-clear.

DAC1

Data address compare 1 write debug event. Set if a write-type DAC1 debug event occurred

(DBCR0[DAC1] = 01 or 11). Functions as write-one-to-clear.

DAC2R Data address compare 2 read debug event.Set if a read-type DAC2 debug event occurred

(DBCR0[DAC2] = 10 or 11). Functions as write-one-to-clear.

DAC2

Data address compare 2 write debug event. Set if a write-type DAC2 debug event occurred

(DBCR0[DAC2] = 01 or 11). Functions as write-one-to-clear.

RET

Return debug event. Set if a return debug event occurred (DBCR0[RET] = 1). Functions as

write-one-to-clear.

49–63

—

Reserved, should be cleared.

61 62 63

Field

Instruction address

—

Reset

All zeros

R/W

SPR

SPR 312 (IAC1); SPR 313 (IAC2)

Figure 6-52. Instruction Address Compare Registers (IAC1–IAC2)

Table 6-35. DBSR Field Descriptions (continued)

Bits

Name

Description

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