MPC8540 datasheet(305/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

Freescale Semiconductor

7-1

Chapter 7

L2 Look-Aside Cache/SRAM

This chapter describes the organization of the on-chip L2/SRAM, cache coherency rules, cache

line replacement algorithm, cache control instructions, and various cache operations. It also

describes the interaction between the L2/SRAM and the e500 core complex.

7.1

L2 Cache Overview

The integrated 256-Kbyte L2 cache is organized as 1024 eight-way sets of 32-byte cache lines

based on 32-bit physical addresses, as shown in Figure 7-1.

Figure 7-1. L2 Cache/SRAM Configuration

The SRAM can be configured with memory-mapped registers as externally accessible

memory-mapped SRAM in addition to or instead of cache. The L2 cache can operate in the

following modes, described in Section 7.2, “Cache Organization”:

•

Full cache mode (256-Kbyte cache)

•

Full memory-mapped SRAM mode (256-Kbyte SRAM mapped as a single 256-Kbyte

block or two 128-Kbyte blocks)

•

Half SRAM and half cache mode (128-Kbyte cache and 128-Kbyte memory-mapped SRAM)

e500 Core

32-Kbyte L1

Instruction Cache

32-Kbyte L1

Data Cache

Core Complex Bus

e500 Core Complex

256-Kbyte

L2 Cache/SRAM

Coherency Module

128

Two 128-Kbyte banks

(8-way)

Independently programmable

as L2 cache or SRAM

RD2

RD1

DOUT

WR IN

RD IN

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