LPC43S30 datasheet(2/156 Pages) NXP

2 / 156 page

LPC43S50_S30_S20

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Product data sheet

Rev. 1.3 — 20 January 2020

2 of 156

NXP Semiconductors

LPC43S50/S30/S20

32-bit ARM Cortex-M4/M0 microcontroller



Cortex-M0 Processor core



ARM Cortex-M0 coprocessor capable of off-loading the main ARM Cortex-M4

application processor.



Running at frequencies of up to 204 MHz.



JTAG



Built-in NVIC.



On-chip memory



Up to 264 kB SRAM for code and data use.



Multiple SRAM blocks with separate bus access. Two SRAM blocks can be

powered down individually.



64 kB ROM containing boot code and on-chip software drivers.



64 bit general-purpose OTP memory.



Two banks (256 bit total) One-Time Programmable (OTP) memory for AES key

storage One bank can store an encrypted key for decoding the boot image.



AES engine for encryption and decryption of the boot image and data with DMA

support and programmable via a ROM-based API.



Clock generation unit



Crystal oscillator with an operating range of 1 MHz to 25 MHz.



12 MHz Internal RC (IRC) oscillator trimmed to 1.5 % accuracy over temperature

and voltage.



Ultra-low power Real-Time Clock (RTC) crystal oscillator.



Three PLLs allow CPU operation up to the maximum CPU rate without the need for

a high-frequency crystal. The second PLL is dedicated to the High-speed USB, the

third PLL can be used as audio PLL.



Clock output.



Configurable digital peripherals



Serial GPIO (SGPIO) interface.



State Configurable Timer (SCTimer/PWM) subsystem on AHB.



Global Input Multiplexer Array (GIMA) allows to cross-connect multiple inputs and

outputs to event driven peripherals like the timers, SCTimer/PWM, and ADC0/1.



Serial interfaces



Quad SPI Flash Interface (SPIFI) with 1-, 2-, or 4-bit data at rates of up to

52 MB per second.



10/100T Ethernet MAC with RMII and MII interfaces and DMA support for high

throughput at low CPU load. Support for IEEE 1588 time stamping/advanced time

stamping (IEEE 1588-2008 v2).



One High-speed USB 2.0 Host/Device/OTG interface with DMA support and

on-chip high-speed PHY (USB0).



One High-speed USB 2.0 Host/Device interface with DMA support, on-chip

full-speed PHY and ULPI interface to external high-speed PHY (USB1).



USB interface electrical test software included in ROM USB stack.



Four 550 UARTs with DMA support: one UART with full modem interface; one

UART with IrDA interface; three USARTs support UART synchronous mode and a

smart card interface conforming to ISO7816 specification.



Up to two C_CAN 2.0B controllers with one channel each. Use of C_CAN controller

excludes operation of all other peripherals connected to the same bus bridge See

Figure 1 and Ref. 2.

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