LPC43S30 datasheet(76/156 Pages) NXP

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LPC43S50_S30_S20

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Product data sheet

Rev. 1.3 — 20 January 2020

76 of 156

NXP Semiconductors

LPC43S50/S30/S20

32-bit ARM Cortex-M4/M0 microcontroller

• Built-in fractional baud rate generator covering wide range of baud rates without a

need for external crystals of particular values.

• Auto baud capabilities and FIFO control mechanism that enables software flow

control implementation.

• Support for RS-485/9-bit/EIA-485 mode.

• USART3 includes an IrDA mode to support infrared communication.

• All USARTs have DMA support.

• Support for synchronous mode at a data bit rate of up to 8 Mbit/s.

• Smart card mode conforming to ISO7816 specification

7.18.3 SPI serial I/O controller

The LPC43S50/S30/S20 contain one SPI controller. SPI is a full-duplex serial interface

designed to handle multiple masters and slaves connected to a given bus. Only a single

master and a single slave can communicate on the interface during a given data transfer.

During a data transfer the master always sends 8 bits to 16 bits of data to the slave, and

the slave always sends 8 bits to 16 bits of data to the master.

7.18.3.1 Features

• Maximum SPI data bit rate 25 Mbit/s.

• Compliant with SPI specification

• Synchronous, serial, full-duplex communication

• Combined SPI master and slave

• Maximum data bit rate of one eighth of the input clock rate

• 8 bits to 16 bits per transfer

7.18.4 SSP serial I/O controller

Remark: The LPC43S50/S30/S20 contain two SSP controllers.

The SSP controller can operate on a SPI, 4-wire SSI, or Microwire bus. It can interact with

multiple masters and slaves on the bus. Only a single master and a single slave can

communicate on the bus during a given data transfer. The SSP supports full-duplex

transfers, with frames of 4 bit to 16 bit of data flowing from the master to the slave and

from the slave to the master. In practice, often only one of these data flows carries

meaningful data.

7.18.4.1 Features

• Maximum SSP speed in full-duplex mode of 25 Mbit/s; for transmit only 50 Mbit/s

(master) and 17 Mbit/s (slave).

• Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National

Semiconductor Microwire buses

• Synchronous serial communication

• Master or slave operation

• 8-frame FIFOs for both transmit and receive

• 4-bit to 16-bit frame

• DMA transfers supported by GPDMA

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