7.6 Typical Characteristics (continued)

at TA = 25°C, VS = (V+) – (V–) = 5.5 V, VIN = (VIN+) – (VIN–) = 0 V, RL = 10 kΩ, CL = 10 pF, VREF = VS / 2, VCM = [(VIN+) +

(VIN–)] / 2 = VS / 2, VOUT = VS / 2 and G = 10 (unless otherwise noted)

Capacitive Load (pF)

0

150

300

450

600

750

900

1050

0

0.5

1

1.5

2

TR03

RISO = 0 :, Overshoot (+)

RISO = 0 :, Overshoot (-)

RISO = 50 :, Overshoot (+)

RISO = 50 :, Overshoot (-)

VS = 5.5 V

G = 30

VOUT = 100 mVPP

Figure 7-43. Small-Signal Overshoot vs Capacitive Load

Capacitive Load (pF)

0

150

300

450

600

750

900

1050

0.4

0.5

0.6

0.7

0.8

TR04

RISO = 0 :, Overshoot (+)

RISO = 0 :, Overshoot (-)

RISO = 50 :, Overshoot (+)

RISO = 50 :, Overshoot (-)

VS = 5.5 V

G = 50

VOUT = 100 mVPP

Figure 7-44. Small-Signal Overshoot vs Capacitive Load

Time (200 µs/div)

-1.5

-1

-0.5

0

0.5

1

1.5

TR05

VIN

VOUT

V+ = 2.75 V

V– = –2.75 V

G = 10

VOUT = 2 VPP

Figure 7-45. Large Signal Step Response

Time (5µs/div)

TR14

V+ = 2.75 V

V– = –2.75 V

G = 10

VOUT = 2 VPP

Figure 7-46. Large Signal Settling Time (Falling Edge)

Time (5µs/div)

TR13

V+ = 2.75 V

V– = –2.75 V

G = 10

VOUT = 2 VPP

Figure 7-47. Large Signal Settling Time (Rising Edge)

Time (200 µs/div)

0

200

400

600

800

1000

-1.5

-1

-0.5

0

0.5

1

1.5

TR06

VIN

VOUT

V+ = 2.75 V

V– = –2.75 V

G = 50

VOUT = 2 VPP

Figure 7-48. Large Signal Step Response

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SBOSAD5 – DECEMBER 2022

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