7.5 Programming

7.5.1 Serial Peripheral Interface (SPI)

The DAC82001 is controlled through a 3-wire serial peripheral interface (SPI) using SYNC, SCLK, and SDIN.

The serial interface operates at up to 50 MHz. The input shift register is 24-bits wide.

Table 7-1 shows the SPI frame format.

Table 7-1. SPI Frame Format

BIT

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

DESC

W

Register Address - Command Byte

16-Bit MSB-Aligned DAC Data

Serial clock SCLK is a continuous or a gated clock. The first falling edge of SYNC starts the operation cycle.

When SYNC is high, the SCLK and SDIN signals are blocked. The device internal registers are updated from the

shift register on the rising edge of SYNC.

7.5.1.1 SYNC Interrupt

For SPI operation, the SYNC line stays low for at least 24 falling edges of SCLK, and the addressed DAC

register updates on the SYNC rising edge. However, if the SYNC line is brought high before the 24th SCLK

falling edge, this event acts as an interrupt to the write sequence. The shift register resets and the write

sequence is discarded. As Figure 7-3 shows, the data buffer contents and the DAC register contents do not

update, and the operating mode does not change.

1

2

24

SCLK

SDIN

DB23

DB0

Invalid or interrupted write sequence

1

2

24

SCLK

SDIN

DB23

DB0

Valid write sequence

SYNC

SYNC

Figure 7-3. SYNC Interrupt

DAC82001

SBASAK3A – SEPTEMBER 2022 – REVISED NOVEMBER 2022

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