3

ICS95V860

0675D—01/07/04

Pin Descriptions

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ICS95V860 is a zero delay buffer that distributes a differential clock input pair (CLK_INC, CLK_INT) to thirteen

differential clock output pairs (CLKT[0:12], CLKC[0:12]) and one differential clock output feedback pair (FB_OUT,

FB_OUTC).The clock outputs are controlled by the input clocks (CLK_INC, CLK_INT), the feedback clocks (FB_INT,

is turned off and bypassed for test purposes.

When the input frequency is less than the operating frequency of the PLL (appproximately 20MHz), the device will enter

a low power mode. An input frequency detection circuit on the differential inputs, independent from the input buffers,

will detect the low frequency condition and perform the same low power features as when the (PD#) input is low.When

the input frequency increases to greater than approximately 20 MHz, the PLL will be turned back on, the inputs and

outputs will be enabled and PLL will obtain phase lock between the feedback clock pair (FB_INT, FB_INC) and the input

clock pair (CLK_INC, CLK_INT).

General Description

(continued)