4

ICS95V860

0675D—01/07/04

Absolute Maximum Ratings

Supply Voltage (VDD & AVDD) . . . . . . . . . . . -0.5V to 3.6V

Ambient Operating Temperature . . . . . . . . . . 0°C to +85°C

Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C

Stresses above those listed under

Absolute Maximum Ratings may cause permanent damage to the device. These

ratings are stress specifications only and functional operation of the device at these or any other conditions above those

listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions

for extended periods may affect product reliability.

The ICS95V860 is able to track Spread Spectrum Clock (SSC) for reduced EMI.

The ICS95V860 is an I

compliant to "The I2C-Bus Specification", version 2.1 January 2000 Philips Semiconductors, except that I2C_SDA

lower. Register bits control the enable for each output pair and a global enable bit (GLOBALEN#) disables all

outputs except the feeback output pair. A low places the disabled output pair in a high impedance state. Outputs

are active during power up and are guaranteed to be at the correct duty cycle and period after the clock

stabilization time.

General Description (Continued)

Device I2C address = 11001, A1, A0, R/W

I

Control

Function

Bit 7

CLK0EN

Output Control

RW

1

Bit 6

CLK1EN

Output Control

RW

1

Bit 5

CLK2EN

Output Control

RW

1

Bit 4

CLK3EN

Output Control

RW

1

Bit 3

CLK4EN

Output Control

RW

1

Bit 2

CLK5EN

Output Control

RW

1

Bit 1

CLK6EN

Output Control

RW

1

Bit 0

CLK7EN

Output Control

RW

1

I

Control

Function

Bit 7

CLK8EN

Output Control

RW

1

Bit 6

CLK9EN

Output Control

RW

1

Bit 5

CLK10EN

Output Control

RW

1

Bit 4

CLK11EN

Output Control

RW

1

Bit 3

CLK12EN

Output Control

RW

1

Bit 2

Reserved

Reserved

RW

0

Bit 1

Reserved

Reserved

RW

0

Bit 0

GLOBALEN#

Output Control

RW

0

NOTE: GLOBALEN# does not tristate the feedback output pair. The PLL continues to run and maintains lock even though all other outputs are tri-stated

Disable = Output in high-impedance state

Enable

01

Enable

Enable

Disable

A6,A7

PWD

A2,A3

A4,A5

Byte 0

Pin #

Name

Type

Disable

Disable

H11,J11

Byte 1

Pin #

A8,A9

B11,C11

D11,E11

F11,G11

Disable

Enable

Disable

Enable

Disable

Enable

Disable

Disable

Enable

Enable

PWD

L8,L9

Disable

Enable

Name

Type

0

1

L6,L7

Disable

Enable

L4,L5

Disable

Enable

L2,L3

Disable

Enable

H1,J1

Disable

Enable

-

Enable

Disable

-

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-

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