TSPC603R datasheet(13/58 Pages) ATMEL

13 / 58 page

5410B–HIREL–09/05

TSPC603R

9.5

Power Dissipation

Notes:

1. These values apply for all valid PLL_CFG[0-3] settings and do not include output driver power (OVDD) or analog supply

power (AV

DD). OVDD power is system dependent but is typically ≤ 10% of VDD. Worst case AVDD = 15 mW.

2. Typical power is an average value measured at VDD = AVDD = 2.5V, OVDD = 3.3V, in a system executing typical applications

and benchmark sequences.

3. Maximum power is measured at V

DD = 2.625V using a worst-case instruction mix.

4. To calculate the power consumption at low temperature (-55°C), use a factor of 1.25.

9.6

Marking

Each microcircuit is legible and permanently marked with at least the following information:

• Atmel logo

• Manufacturer’s part number

• Class B identification if applicable

• Date code of inspection lot

• ESD identifier if available

• Country of manufacture

10. Pin Assignments

10.1

CBGA 255 and CI-CGA 255 Packages

Figure 10-1 (pin matrix) shows the pinout as viewed from the top of the CBGA and CI-CGA

packages. The direction of the top surface view is shown by the side profile of the packages.

Table 9-2.

Power Dissipation

(1)(2)(3)(4) with V

DD/AVDD = 2.5 ±5%V, OVDD = 3.3 ±5%V, GND = 0V, 0°C ≤ T

C ≤ 125°C

CPU Clock Frequency

Cerquad 240 Package

CBGA 255, HiTCE CBGA 255 and CI-CGA 255

Units

166 MHz

200 MHz

166 MHz

200 MHz

233 MHz

266 MHz

300 MHz

Full-on Mode (DPM Enabled)

Typical

2.1

2.5

2.1

2.5

3.5

Max

3.2

4.6

5.3

Doze Mode

Typical

1.5

1.7

1.5

1.7

1.8

2.1

Nap Mode

Typical

100

120

100

120

140

160

180

Sleep Mode

Typical

110

123

135

150

Sleep Mode-PLL Disabled

Typical

606060

Sleep Mode-PLL and SYSCLK Disabled

Typical

252525

Maximum

100

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