TSPC603R datasheet(21/58 Pages) ATMEL

21 / 58 page

5410B–HIREL–09/05

TSPC603R

Global

GBL

If output, a transaction is global

If input, a transaction must be snooped by the 603R

I/O

Hard Reset

HRESET

Initiates a complete hard reset operation

Input

Interrupt

INT

Initiates an interrupt if bit EE of MSR register is set

Input

Factory Test

LSSD_MODE

LSSD test control signal for factory use only

Input

L1_TSTCLK

LSSD test control signal for factory use only

Input

L2_TSTCLK

LSSD test control signal for factory use only

Input

Machine Check

Interrupt

MCP

Initiates a machine check interrupt operation if the bit ME of MSR register and

bit EMCP of HID0 register are set

Input

PLL Configuration

PLL_CFG[0-3]

Configures the operation of the PLL and the internal processor clock frequency

Input

Power supply indicator

VOLTDETGND

Available only on BGA package

Indicates to the power supply that a low-voltage processor is present.

Output

Quiescent

Acknowledge

QACK

All bus activity has terminated and the 603R may enter a quiescent (or low

power) state

Input

Quiescent Request

QREQ

Is requesting all bus activity normally to enter a quiescent (low power) state

Output

Reservation

RSRV

Represents the state of the reservation coherency bit in the reservation

address register

Output

System Management

Interrupt

SMI

Initiates a system management interrupt operation if the bit EE of MSR register

is set

Input

Soft Reset

SRESET

Initiates processing for a reset exception

Input

System Clock

SYSCLK

Represents the primary clock input for the 603R, and the bus clock frequency

for 603R bus operation

Input

Test Clock

CLK_OUT

Provides PLL clock output for PLL testing and monitoring

Output

Transfer Acknowledge

A single-beat data transfer completed successfully or a data beat in a burst

transfer completed successfully

Input

Timebase Enable

TBEN

The timebase should continue clocking

Input

Transfer Burst

TBST

If output, a burst transfer is in progress

If input, when snooping for single-beat reads

I/O

Transfer Code

TC[0-1]

Special encoding for the transfer in progress

Output

Test Clock

TCK

Clock signal for the IEEE P1149.1 test access port (TAP)

Input

Test Data Input

TDI

Serial data input for the TAP

Input

Test Data Output

TDO

Serial data output for the TAP

Output

Transfer Error

Acknowledge

TEA

A bus error occurred

Input

TLBI Sync

TLBISYNC

Instruction execution should stop after execution of a tlbsync instruction

Input

Test Mode Select

TMS

Selects the principal operations of the test-support circuitry

Input

Test Reset

TRST

Provides an asynchronous reset of the TAP controller

Input

Transfer Size

TSIZ[0-2]

For memory accesses, these signals along with TBST indicate the data

transfer size for the current bus operation

I/O

Table 10-6.

Signal Index for Cerquad, CBGA 255, HiTCE CBGA 255 and CI-CGA 255 Packages (Continued)

Signal Name

Abbreviation

Signal Function

Signal

Type

TSPC603R Datasheet(PDF) 21 Page - ATMEL Corporation

TSPC603R Datasheet(HTML) 21 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58

Datasheet Download

Link URL