AP64060

Document number: DS44123 Rev. 2 - 2

10 of 18

www.diodes.com

August 2022

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AP64060

Application Information

1

Pulse Width Modulation (PWM) Operation

The AP64060 device is a 4.5V-to-340V input, 600mA output, EMI friendly, fully integrated synchronous buck converter. Refer to the block diagram

in Figure 4. The device employs fixed-frequency peak current mode control. The internal 2MHz

clock’s rising edge initiates turning on the

integrated high-side power MOSFET, Q1, for each cycle. When Q1 is on, the inductor current rises linearly and the device charges the output

capacitor. The current across Q1 is sensed and converted to a voltage with a ratio of RT via the CSA block. The CSA output is combined with an

internal slope compensation, SE, resulting in VSUM. When VSUM rises higher than the COMP node, the device turns off Q1 and turns on the low-

side power MOSFET, Q2. The inductor current decreases when Q2 is on. On the rising edge of next clock cycle, Q2 turns off and Q1 turns on.

This sequence repeats every clock cycle.

The error amplifier generates the COMP voltage by comparing the voltage on the FB pin with an internal 0.8V reference. An increase in load

current causes the feedback voltage to drop. The error amplifier thus raises the COMP voltage until the average inductor current matches the

increased load current. This feedback loop regulates the output voltage. The internal slope compensation circuitry prevents subharmonic

oscillation when the duty cycle is greater than 50% for peak current mode control.

The peak current mode control, integrated loop compensation network, and built-in 4ms soft-start time simplifies the AP64060 footprint as well as

minimizes the external component count.

2

Pulse Frequency Modulation (PFM) Operation

In heavy load conditions, the AP64060 operates in forced PWM mode. As the load current decreases, the internal COMP node voltage also

decreases. At a certain limit, if the load current is low enough, the COMP node voltage is clamped and is prevented from decreasing any further.

The voltage at which COMP is clamped corresponds to the 200mA PFM peak inductor current limit. As the load current approaches zero, the

AP64060 enters PFM mode to increase the converter power efficiency at light load conditions. When the inductor current decreases to 50mA, zero

cross detection circuitry on the low-side power MOSFET, Q2, forces it off. The buck converter does not sink current from the output when the

output load is light and while the device is in PFM. Because the AP64060 works in PFM during light load conditions, it can achieve power

efficiency of up to 82% at a 5mA load condition.

The quiescent current of the AP64060 is 90

μA typical under a no-load, non-switching condition.

3

Enable

When disabled, the device shutdown supply

current is only 1μA. When applying a voltage greater than the EN logic high threshold (typical 1.21V,

rising), the AP64060 enables all functions and the device initiates the soft-start phase. The EN pin is a high-voltage pin and can be directly

connected to VIN to automatically start up the device as VIN increases. The AP64060 has a built-in 1ms soft-start time to prevent output voltage

overshoot and inrush current. When the EN voltage falls below its logic low threshold (typical 1.10V, falling), the internal SS voltage discharges to

ground and device operation disables.

The EN pin can also be used to program the undervoltage lockout thresholds. See Undervoltage Lockout (UVLO) section for more details.

4

Adjusting Undervoltage Lockout (UVLO)

Undervoltage lockout is implemented to prevent the IC from insufficient input voltages. The AP64060 device has a UVLO comparator that monitors

the input voltage and the internal bandgap reference. The AP64060 disables if the input voltage falls below 3.8V. In this UVLO event, both the

high-side and low-side power MOSFETs turn off.

For applications requiring higher VIN UVLO threshold voltages than is provided by the default setup, an external resistor R3 added in series to the

EN pin

along with an internal 480kΩ configures the VIN UVLO threshold voltages as shown in Figure 24.